Albany Hosts Yield Control Short Course
Laura Peters, Senior Editor -- Semiconductor International, 9/1/2002
The School of
NanoSciences and NanoEngineering at the University at Albany (Albany, N.Y.) will host a course, "Integrated Circuit Fabrication and Yield Control," on Oct. 1-2. The course will describe the tools and processes used in a step-by-step build sequence typical of current logic chip manufacturing. At every key step from shallow trench isolation to multilevel interconnects, the seminar will detail with SEM illustrations the processes, problems and defects encountered. It will be taught by Albany NanoTech staff member Ernest Levine, who spent 25 years at IBM.
The two-day course will begin by describing the characteristics of wafer processing tools and the methodologies used to fabricate logic field-effect transistors and DRAM devices. Yield control strategies will be presented in concert with lithographic controls, inspection methodologies and in-line testing strategies. The course will include yield control strategies and methodologies used to ascertain root cause of problems, enabling informed decisions about a process or problem anywhere in the IC build process. The instructor will present examples of defects encountered during various process steps including dual-damascene copper fabrication and low-k dielectric processing. Cost is $900. For more information, visit www.albanynanotech.org/info/events/index.cfm.
For additional information on yield management, go to www.semiconductor.net/yield.
