Flip-Chip Packaging Moves into the Mainstream

Originally introduced by IBM more than 30 years ago, flip-chip packaging is by no means a new technology. But until recently, flip-chip technology has been restricted to high-end devices and niche applications. Today, demand for flip-chip packaging is on the rise, as the technology is being embraced for a broader range of applications and implemented in a wider variety of package types. At the same time, flip-chip presents manufacturers with a new array of challenges, making it critical for them to leverage the expertise of back-end subcontractors to provide packaging, assembly and test services for this complex technology.

Flip-chip is not a specific package or package type, but rather a method of connecting the die to the package carrier. Traditionally, this interconnection was made using wire, hence the term wire-bond packaging. In flip-chip, the interconnection is made using a conductive bump that is placed on the die surface (Fig. 1). The bumped die is then flipped over to connect directly to the carrier, thus the term flip-chip.

Flip-chip offers a variety of benefits compared with traditional wire-bond packaging, including superior thermal and electrical performance, the highest I/O capability, substrate flexibility for varying performance requirements, well-established process equipment expertise, proven construction, and reduced form factors. Of these benefits, three primary customer requirements are driving demand for this technology: thermal performance, electrical performance and reduced form factors.

1. Flip-chip offers a variety of benefits compared with traditional wire-bond packaging, including superior thermal and electrical performance, and reduced form factors.

The thermal performance of flip-chip packaging is clearly superior to that of conventional wire-bond packaging. Many of today's electronic devices such as ASICs, microprocessors and systems-on-a-chip (SOCs) dissipate 10-25 W, much more than the 5-10 W that can be handled by a thermally enhanced wire-bond ball grid array (BGA) package. In contrast, a flip-chip package can generally tolerate dissipation of 25 W, depending on the operating environment and thermal requirements (maximum junction temperature, ambient temperature and air flow), and package parameters such as use of an external heat sink, package and die size, substrate layer count and ball count.

The outstanding thermal performance of flip-chip is accomplished by its heat spreader construction, which provides low thermal resistance. Heat is dissipated through thermal balls, and internal and external heat sinks. A low θ_jc (junction to case) can be achieved by contact between the heat spreader lid and the die. A thin bond line of thermal grease is typically used between heat sink lid and die to improve the thermal path, allowing the heat to escape from the package more easily. To further improve the thermal performance, an external heat sink can easily be attached to the exterior lid to capitalize on the package's low u_jc.

Another key benefit of flip-chip packaging is its electrical performance. By eliminating the wire bonds, which can act as a bottleneck in the package, flip-chip offers improved electrical performance. Many of today's electronic devices are operating at high frequencies, and signal integrity is therefore an important consideration. In the past, 2-3 GHz was the upper limit of most packages. In contrast, flip-chip can easily support frequencies of 10 GHz and up to 40 GHz frequencies depending on substrate technology.

There are two primary environments for flip-chip implementation: stripline and microstrip. Offering optimal electrical performance, a stripline environment is the ideal platform for signal referencing in flip-chip designs. Because the typical substrate layer count is six or more, the increased layer count enables layer stack-up/routing flexibility. In a stripline environment, one signal conductor layer is sandwiched between two reference plane layers — one plane layer on top and one plane layer on the bottom.

2. A stripline structure can provide a good return current path for high-speed signals and reduce crosstalk and noise coupling, while a low-dielectric-constant substrate material enables good signal coupling.

3. The benefits of a microstrip structure include controlled signal impedance, reduced signal crosstalk and reduced signal inductance.

Because of the package construction of the flip-chip package, the package footprint can be minimized while the I/O count can be maximized. As stated earlier, the die in flip-chip is attached directly onto the substrate using eutectic solder bumps. The die solder bumps are reflowed onto the topside of the substrate. Conversely, solder balls are reflowed onto the bottom side of the substrate. This package construction (multi-layer, blind/buried vias, fine-pitch routing and the ability to successfully address high-density routing requirements from the bump matrix) allows for the creation of a full package ball matrix on the bottom side. In addition to a full ball matrix configuration, the standard ball pitch for flip-chip is 1.0 mm. The reduced ball pitch and full ball matrix configuration allows for a higher ball count in a reduced package size.

Because of their array pattern, flip-chip packages support the highest possible I/O counts — up to 1500. Therefore, designs with I/O counts of 800 and more are perfect candidates for flip-chip. In this case, the package involves a minimum of 800 wires, which not only leads to considerable assembly time but also to the potential for a reliability problem. Because of the density required for wire-bond, the design often can become unfeasible or extremely difficult to manufacture because of the quantity of wires. This can reduce yield and manufacturability. In addition, with I/O counts of 800 or more, the package will contain extremely long wire lengths, which diminishes electrical performance.

Other variables to consider when choosing a flip-chip design include:

• Trace width and spacing: The die bump pitch dictates the escape width and spacing from the die area. The bump pitch and the I/O counts are typically fixed. Layer counts are flexible but typically minimized (as long as performance issues are met) to reduce the substrate cost. The aggressiveness of the trace and spacing is determined by all of these factors. In addition, impedance control is accomplished in part by the trace width and spacing. If crosstalk is an issue, trace space is maximized to reduce crosstalk.
• Blind and buried via/via drill capabilities: To minimize the via pad diameter, vendors'drill capabilities must be accurate and they must use a laser drill. In addition, to satisfy performance/routing requirements and minimize the via area usage typical of through-hole vias, blind and buried vias with small drill and pad diameters are required. This is critical as the bump pitch reduces. To successfully escape aggressive bump pad pitches, microvia drill and pad features are required.
• Core via limitations: Large core via drill holes and pad diameters limit placement densities. The route density is far too high near the die to allow for core via placement. Typically, because of the large via size, the core via placement follows the ball pad pitch and is located directly over the ball pad. This makes good sense because the route density is low, and the vias are spaced enough to allow for adequate metal plane coverage. If core vias are placed too close together, the area will be void of plane metal due to typical plane-metal-to-via clearance rules.
• Stackable vias: The next generation of via construction in organic flip-chip substrates. Stackable vias allow for the substrate construction whereby large core vias and their inherent limitations can be eliminated. With stackable vias, fine route densities can be accommodated on the core layers; this would improve routing flexibility and electrical performance, as well as reduce layer counts. Stackable via technology is relatively new, and will certainly become more popular as routing and performance requirements increase.

Another key consideration is layer counts and configurations involved in the design. Organic flip-chip designs typically have four to 10 layers, whereas typical wire-bond products have one to four layers. The increase in layer counts adds to the flexibility and ability to achieve routing environments suitable for high-speed critical signals.

In the future, the material sets, substrate construction and process will continue to evolve. Suppliers will continue to improve substrate technology, routing densities, layer structure and other factors — all of which affect performance. Process geometries will continue to shrink. New software will become available to help automate the design process.

All of these technical improvements are destined to enhance the growing acceptance and popularity of flip-chip packaging. At the same time, customers will continue looking to flip-chip as the packaging solution of choice for many wireless, networking and communications applications in which performance and compactness are critical considerations.