Photoresist Trimming: Etch Solutions to CD Uniformity and Tuning

Production lithography processes using 248 nm exposure tools can be used to develop photoresist (PR) patterned masks with critical dimensions (CDs) typically down to 180 nm at best. Advanced exposure tools and resist formulas are required to routinely achieve CDs of 150 nm or less. However, logic applications often require smaller gate width dimensions, necessitating further trimming of the developed PR before the resist pattern is transferred to the underlying film. Hence, conventional lithography is used to spin, expose and develop photoresist patterns, and the linewidths of the resist patterns are subsequently reduced through plasma etching.

Figure 1 illustrates an example of the use of PR trimming to define a polysilicon gate. In this example, a hardmask (typically silicon dioxide or oxynitride) is used, and a nominal 160 nm polysilicon gate is reduced to 100 nm.

A caveat is that resist trimming does not enable miniaturization of circuits by increasing feature density. The reduction in resist linewidth is accompanied by a corresponding increase in the spacing between the lines, thereby preserving the pitch. For this reason, the process cannot be used, for example, to obtain more densely packed DRAMs. However, reduction of the polysilicon gate length through resist trimming enables fabrication of faster MOS logic circuits without requiring advanced lithography.

A polysilicon gate etch process can be integrated into production in several ways. For example, the etch can be done before (as in Fig. 1 ) or after resist strip. Some processes use a bottom antireflective coating (BARC) layer under the polysilicon to improve resolution during exposure, and others employ a dielectric ARC (DARC) layer. If the BARC material is inorganic, it is etched at the same time as the hardmask. If the BARC material is organic, it is typically etched through and removed when the resist is stripped. The resist trim process should be adaptable to these and other process flows.

1. In this example, a hardmask is used for resist trimming, reducing a poly-Si gate from 160 to 100 nm.

The aim of the photoresist etch step, depending on the process flow, may range from horizontal trimming and minimal height loss at one end of the spectrum to reduction of photoresist height with minimal trimming. Thus, it is crucial to develop processes that provide independently controllable vertical and lateral resist etch rates.

The best achievable vertical-to-lateral etch rate ratio (V/L) corresponds to perfectly isotropic etching, where the vertical and horizontal etch rates are equal (V/L=1). The geometry of the resist features implies that, given the same horizontal and vertical etch rates, the linewidth shrinks twice as much as the resist thins after any specified etch period, and the ratio of resist thickness loss to linewidth reduction is 1:2. For sufficient resist to remain for masking during a subsequent etching of a hardmask, the V/L ratio should be as close as possible to 1:1.

V/L can be controlled by taking advantage of inductively coupled plasmas, which offer independent control of ion flux and ion energy through power supplied respectively to the top and bottom electrodes (Fig. 2b). Conventional plasma processes require highly anisotropic etch, which is achieved easily through high ion flux and energy. Capacitively coupled plasmas (Fig. 2a) suffice for such applications. However, resist trim requires lateral etch while minimizing vertical etch and, hence, require the decoupling of ion energy and ion flux. Resist trim applications typically employ relatively low bias power set points, and small variations in bias power can affect the V/L ratio. Controlling bias voltage (BV) instead of bias power allows a more direct control of ion energy, while minimizing the effects of systematic bias power variations.

2. Schematic representations depict a) a capacitively coupled plasma source, and b) an inductively driven plasma source.

Minimizing resist loss is especially critical for process flows in which a hardmask is not used. The ratio of vertical-to-horizontal resist etch rates can be optimized by controlling process parameters such as BV and feed gas ratios.

Etch duration also needs to be addressed while designing resist trim recipes. Etch steps need to be short enough to provide acceptable throughput, but long enough to provide good control of resulting feature profiles. For example, it would be difficult to control a 10 sec etch within ±1 sec, but a 150 sec etch could conceivably set throughput back considerably. A nominal etch rate of ~20-60 nm/min and an etch time of ~30 sec is a good tradeoff between high throughput and the ability to precisely control the etch time and features. We have achieved controllable etch rates of 40-60 nm/min by optimizing the feed gas flows and BV applied at the wafer.

Another effect that needs to be controlled and minimized during PR etching involves aspect-ratio-dependent etching that leads to iso-dense profile microloading. The initial depth/width aspect ratio (AR) of the spaces between resist lines can affect feature profiles resulting from the resist etch process. For example, when there is a high pattern density corresponding to features with large ARs, there is a tendency for isolated resist lines to be etched more rapidly than lines in densely patterned regions, especially when the etch process operates in a neutral limited regime. In contrast, when etching PR on BARC stacks, it is possible to operate in a process window where redeposition of etched BARC can cause more CD growth on the isolated resist lines than the corresponding dense regions.

In general, for an AR greater than 3:1, variation in trimmed feature CDs between the isolated and dense lines is likely. For applications that have been characterized so far, the AR is less than 1:1, and no CD variation due to iso-dense profile microloading has been observed. Iso-dense CD control is typically an issue when greater etchant surface coverage in the isolated regions causes faster etching in these areas than in the corresponding densely patterned areas. It is possible to reduce this effect by employing additives in the plasma that can promote polymer deposition on the isolated lines exceeding deposition on the dense lines, thereby slowing down the trim preferentially in the isolated regions, yielding reduced or even tunable iso-dense loading.

For example, an application on Lam's 2300 Versys silicon etch system required trimming PR lines on 300 mm wafers by more than 50 nm. An HBr/O₂ chemistry was chosen for this application because of its fast trim rate. Through a matrix of experiments, we determined that adjustments to pressure and TCP¹ source power minimized the iso-dense loading effect. Under these conditions, after trimming ~55 nm, the CD bias uniformity (3σ) was 9 and 10 nm at the nested and isolated lines, respectively. In addition, the iso-dense CD bias loading was ~7 nm. Furthermore, the areas in the center were trimmed more than those at the edge of the wafer, leading to center-to-edge loading. Altering the source power and changing the residence time did not yield improvement in center-to-edge uniformity and iso-dense tuning capability.

Hence, experiments were conducted with novel additives to the HBr/O₂ chemistry in small proportions. We hypothesized that the additives would lead to formation of polymer film on the sidewalls, rendering the profiles more uniform. In addition, the possibility existed of a regime in which the polymer deposition on the isolated lines would exceed that on the dense lines, thereby slowing down the trim preferentially in the isolated regions, leading to less iso-dense loading. In PR trim experiments, polymer-forming additives helped to reduce and even invert the center-to-edge loading on the 300 mm wafers tested, while also improving the uniformity of trim and reducing iso-dense loading.

Uniformity across the wafer must also be maximized to reduce CD variation. Across-wafer CD uniformity is influenced by ion and neutral transport in the plasma chamber, and is determined by hardware design aspects such as top vs. bottom feed, center vs. outside inlet, location and symmetry of pumping outlets, and other factors, including wafer-to-wafer variations. Computational fluid dynamics (CFD) simulations and modeling and analysis of plasma power deposition have been used in conjunction with experiments to optimize hardware design. These studies provided guidelines toward obtaining gas injectors that distribute reactant and product flows more evenly across the wafer and rf coils that enable uniform power deposition.

In addition, process solutions to trim uniformity have been explored. For example, uniformity worsens with decreasing Cl₂/O₂ ratio in the feed gas. When the concentration of oxygen in the plasma is very high, most of the PR trimming occurs through an isotropic spontaneous chemical etching mechanism. Addition of Cl₂ to the plasma enhances anisotropic ion-driven mechanisms, such as physical sputtering and ion-enhanced etching, which improve trim uniformity.

3. Graphs show a comparison of CD evolution for isolated and dense linewidths (left) and CD bias, across-wafer CD bias uniformity, and center-to-edge CD variation (right) for resist trim with Cl2/O2.

Both sidewall roughness and scum contribute to gate length variation. Often a special oxygen plasma de-scum process is used to smooth sidewalls and remove resist scum. Additional benefits of PR trimming include reduction or removal of the photoresist foot or scum at the bottom of a resist wall, and reduction of the resist sidewall roughness.

Resist trim processes implemented in Lam high-density plasma etch systems typically employ a mixture of Cl₂ or HBr with O₂. Rf power at 13.56 MHz is supplied to generate the plasma; power is supplied separately to bias the substrate (BV). Process variables include total pressure, O₂/Cl₂ (or HBr) ratio, and plasma power and wafer BV.

Resist trimming proceeds by chemical etching (driven by the concentration of reactive neutrals) and by ion-driven chemical sputtering and physical sputtering mechanisms. The chemical etch component reduces the linewidth, smoothes sidewalls, and thins the resist. The sputtering component removes the resist foot and thins the resist, but does not shrink the linewidth. Increasing the source power increases the concentration of chemically reactive species and the ion density. Increasing the BV on the substrate increases the ion bombardment energy and, hence, the sputtering effects. An ideal trim process must achieve a controlled balance among these mechanisms to produce smooth, vertical profiles without losing too much resist thickness for a given process scheme.²

Determining the appropriate trim process for any application requires an understanding of the effect of each process knob. A study was conducted employing Cl₂/O₂ chemistry on 200 mm wafers. An experimental matrix was implemented for the following parameters: total pressure, BV, TCP power, and O₂/Cl₂ ratio. We determined that vertical rate, trim rate, vertical rate uniformity, trim uniformity, and the V/L rate ratio could be controlled to optimize the process by adjustments to these parameters. For example, increasing the vertical etch rate involves adjustments to four of the parameters. In fact, each process effect studied involved adjusting two to four of the parameters to achieve desired results on the wafer.

The experimental results were coupled with chamber diagnostic data and published work characterizing dominant mechanisms³ to develop and calibrate a semi-empirical model for the surface kinetics and chemistry during the resist trim process. This model was implemented on a feature profile simulator. The calibration enables prediction of the impact of changes in recipe parameters such as source power, BV, and percent Cl₂ over a wide range of process conditions on ion and neutral fluxes, ion energy, etc., which are input to the profile simulator.

4. Trim (horizontal etch) rate and resist thinning (vertical etch) rate vs. total pressure for a 1:3 (top) and 3:1 (bottom) O2:Cl2 flow ratio at two BV levels. The trim rate is unaffected by BV, and all rates decrease with increasing pressure. Comparison of the two graphs shows that rates increase with an increased O2:Cl2 flow ratio.

The details of the semi-empirical model and its calibration are described elsewhere.⁴ Figure 4 shows the dependence of the resist thinning (vertical etch) rate and the trim (horizontal etch) rate on pressure for different O₂/Cl₂ flow ratios; the profile simulator is calibrated to reflect the experimental observation that trim rate is independent of BV. Both the trim rate and the resist thinning rate decrease slightly with increasing pressure, but both rates are increased by increasing the O₂/Cl₂ flow ratio.

To evaluate the iso-dense profile effect, the experiment matrix included three feature sizes, three levels for BV, and four O₂/Cl₂ ratios. The resist thinning rate increased with BV, while the trim rate remained relatively insensitive to BV, linewidth and pattern density. Experiments on the effect of the O₂/Cl₂ ratio on the trim rate and resist thinning rate for various linewidths and densities showed that pure oxygen is not a suitable etch gas because the ratio of vertical etch rate to trim rate is too high. Adding chlorine provides better control over the thinning rate.

In experiments of resist lines that were trimmed at a low BV, the foot initially present at the base of the line was removed after a 30 sec etch. After a 90 sec etch, the initial linewidth was reduced by 50%, and the resist thickness was reduced by about 37%. Increasing the BV increases the thinning rate, and sputtering becomes the dominant etch mechanism, leading to faceting of the top corners of the resist line.

5. Trimming of 160 nm lines at 10 W (left) and 40 W (right) BP. The green dashed outline represents the original resist profile; the black dashed lines show the successive changes in profile. At higher BP, the rate of resist thinning is enhanced.

6. Comparison of simulated and experimental profiles after a 90 sec trim of a 160 nm line at 10 W BV. The green outline shows the original resist profile.

This study demonstrates that resist lines can be trimmed using an O₂/Cl₂ discharge in a high-density inductively coupled plasma chamber, where the original resist is spun using current production lithography techniques. Controlled trim rates in the 40-60 nm/min range were achieved by optimizing the O₂/Cl₂ ratio and bias voltage at the wafer. The microloading effect was negligible for resist line aspect ratios of ~1:1. In addition, after resist line trim and etching of the underlying hardmask, the 3σ CD variation across the wafer of the final 100-nm-wide lines was <7 nm. For logic applications, the resist trim process offers a means to shrink gate length without the need for advanced lithography.

Some applications would benefit from a trim process such as this, where tuning can compensate for previous or subsequent process biases. A good trim process should enable varying the center-to-edge and iso-to-dense trimming rates. These possibilities, plus the capability to trim gate length lines down to 60 nm, are being vigorously pursued. Implementing such processes requires a direct correlation between the reactor knobs and the feature profiles of the etched wafers. Plasma and surface diagnostics coupled with physics-based simulation tools can help achieve these goals.