Bluetooth: Poster Child for the SiP
Eric Bogatin, Contributing Editor -- Semiconductor International, 9/1/2002
You're in an amusement park. You have three screaming, excited kids jumping up and down around you. You suddenly realize you're supposed to have four kids with you. In the blink of an eye, your 5-year-old has wandered off and is lost in the crowd.
Technology may be around the corner to prevent this sort
of common disaster. Bluesoft Inc. (San Francisco) has developed a patent-pending distance-measurement and location-finding technology compatible with the Bluetooth interface. If your child is wearing an equipped wristwatch, you could be alerted if he or she walks off more than a present distance.
Wireless local area networks (LANs) are proliferating. The current popular standard, 802.11b, allows communication to hundreds of feet. The Bluetooth standard, sharing the same 2.4 GHz region of the spectrum, is specifically limited to 30 ft. The shorter range for Bluetooth means lower power, fewer parts, smaller form factor and possible integration into more personal appliances. It also is extremely cost-driven. The Bluetooth Special Interest Group (SIG), which promotes the qualification of all products to the Bluetooth standard for interoperability, lists more than 680 different products that have been qualified to date.
Though many products have a different partitioning between the silicon, packages, passives and board, there is one common theme for virtually all approaches — the use of system-in-a-package (SiP) approaches. A SiP is one or more chips in a small package, sometimes with passives, either as discrete or embedded.
The key features of Bluetooth modules that drive the proliferation of partitioning choices is the need for both rf and digital functions in close proximity, with small footprint and at low cost. A different balance to the partitioning trade-offs drive different "right" answers.
Motorola recently announced a pair of Bluetooth modules. Each module balances a difference set of trade-offs, but both take advantage of SiP solutions. In both approaches, all the rf functions are integrated on a single BiCMOS chip.
Three qualities define the sensitivity of the rf module: the gain, impedance matching and the frequency response, according to John Breeden, wireless personal area network product manager at Motorola (Phoenix). "While the Bluetooth spec is for 70 dB sensitivity and many products achieve 80 dB, BiCMOS can give better than 80 dB. When there are many users, higher sensitivity will translate to less interference." The use of BiCMOS for higher rf sensitivity virtually eliminates the possibility of a cost-effective system-on-a-chip (SoC) solution.
| Two Bluetooth packaging solutions: LTCC (left) and stacked die (right). |
For use in products that do not provide the digital functionality, the baseband functions are integrated on a CMOS chip that is packaged with the rf chip. "Real estate is expensive, and we wanted to achieve the smallest footprint possible," said Jim Kleffner, Bluetooth product manager at Motorola. "The smallest footprint solution is a stacked, two-die approach."
In the two-chip Bluetooth module, the substrate is just a simple BGA laminate with 100 I/Os off the bottom. To save real estate, no passives are in the package; they are all added at the board level. One of the problems with stacking an rf chip and a digital baseband chip is the potential interference from the overlapped wire bonds. According to Kleffner, designs were tried with the rf chip on top and on the bottom. The best results were with the smaller rf chip on the bottom.
With the rf chip on the bottom of the stack, high-frequency wire bonds can be kept short and recessed away from the noisy digital wire bonds of the baseband chip. To mount the larger digital chip on top, a small silicon interposer rests between the rf chip and the digital chip. This is the configuration that will ship later this year.
As Bluetooth applications proliferate and trade-offs are made between the silicon, package, passives and board, the use of SiPs will offer a powerful building block to optimize the cost, functionality and form factor.
For additional information on semiconductor packaging, go to www.semiconductor.net/assembly