Plasma and Process Damage: Results From P2ID 2002

Terence B. Hook, IBM Microelectronics, Essex Junction, Vt. -- Semiconductor International, 8/1/2002

At a Glance This report from the recent P2ID conference reviews recent work and provides a prognosis for the future directions of research.

Engineers and scientists of many disciplines converged on Maui, Hawaii, in June to review the latest progress in understanding and controlling process-induced damage. At the 7th International Symposium on Plasma- and Process-Induced Damage (P2ID), researchers from Asia, the United States and Europe met to discuss these issues. Some of the latest information on tool design, the role of ultraviolet radiation in plasma processes, high- and low-k technologies, and other topics was presented. One session was devoted to negative bias temperature instability (NBTI), which is emerging as a serious limitation to reliability in modern technologies.

Radiation effects in plasma processes

In addition to massive charged and neutral particles, there is also a rich mixture of photons of various energies in a plasma, most notably in the ultraviolet (UV) to extreme ultraviolet (EUV) range. These photons have been shown to play a variety of roles in damaging mechanisms. It has been known for some time that an insulating layer is not sufficient to protect an underlying conductor from accumulating charge,¹ as illustrated in Figure 1. A report from Stanford University postulated a UV-induced photoconduction mechanism that takes into account the very small hole mobility in oxide to produce an enhancement of the electric field in the oxide and increase the photoconduction.² The oxide conduction as modeled by Stanford is of an appropriate magnitude to explain damage through a film of 5000 Å or more, in agreement with experimental data.

PHOTOCONDUCTION MECHANISM

1. Schematic illustrations of photoconduction mechanism by which gates may be damaged even when covered with thick insulating oxide.

Okigawa et al considered the direct damaging effect of the UV.³ They demonstrated that, with a time-modulated plasma, the UV-induced current could be dramatically reduced, while leaving the electron density reasonably constant. The process with less UV radiation was shown to produce less dark current in a CCD imaging chip.

A relationship between plasma-generated UV and failing EPROM cells was also shown.⁴ In that report, the role of the CO in the etch chemistry was shown to correlate to the intensity of UV radiation, and thence to the amount of conduction through the EPROM oxide during the process. However, there may also be positive effects of exposure to photon radiation. Enhanced photoconduction may serve to bleed off charging current,⁵ and Professor T.P. Ma of Yale University reported on an intriguing phenomenon in which the application of photon energy enhances the annealing of damaged oxide.⁶

Tool design

Neutral beams can eliminate many of the problems associated with plasma etching if beam current of sufficient magnitude for practical processing can be generated. Researchers from Ebara and Tohoku University reported on a system that produces a 98%-efficient neutralized beam from negative ions by passing the ions through a grounded carbon screen (Fig. 2).⁷ A high silicon etch rate of 6000 Å/min and an anisotropic etch profile was shown, as was the effectiveness of the neutral-beam process in eliminating charging damage. A special diagnostic cathode used for 300 mm etch chamber scale-up was described.⁸ As it is well known that uniformity of the potential is a sine qua non for preventing damage, a set of probe points was distributed spatially across the cathode. Leads from these test points were plumbed through the pedestal and into a lowpass filter to measure the dc potential. In this way the design of the tool and process conditions could be determined to minimize the potential difference across the wafer. Data from these special cathodes indicated that the 300 mm tool was capable of uniformity equivalent to the 200 mm tool.

NEUTRAL-BEAM TOOL

2. Schematic illustration of neutral-beam tool configuration.

Low-k materials and damage

Reducing the wiring capacitance is of great importance not only to continue improving the performance of semiconductor products, but also to address the critical issue of increasing power density and the increasing demand for low-power chips for portable applications. Many new materials are still under consideration for these films,⁹ but the immunity to damage for these materials has barely been addressed yet. Yunogami et al reported on a rapid SPV (surface photo voltage) technique to measure the characteristics of a damaged low-k film.¹⁰ The authors have empirically correlated a reduction in hysterisis in the surface photovoltage/voltage behavior to an increase in the k value of SiLK and MSQ. In this case, the films were damaged by exposure to oxygen and nitrogen-containing plasmas. Authors from Toshiba reported on changes in lateral line-line conductivity induced by various plasma treatments of low-k SiOC.¹¹ Whereas O₂ ashing of spin-on SiOC was shown to increase the leakage current as compared with H₂O ashing, PECVD SiOC was not similarly affected, indicating a greater robustness to plasma-induced damage (Fig. 3).

OXYGEN ASH EFFECT

3. Effect of oxygen ash on the conductivity of low-k insulating films.

Negative bias temperature instability

The NBTI phenomenon, although known for many years, has recently emerged with greater technological importance than ever before.¹² NBTI, in which positive charge and interface traps are created under the influence of negative gate bias and thermal energy, is known to be dependent on trace "contaminants" of the oxide, such as nitrogen and fluorine, and moisture-related elements such as hydrogen and OH. The work of Lee et al confirmed these observations.¹³ Tan et al compared the NBTI results on oxides in which nitrogen was introduced by plasma nitridation and by thermal nitridation.¹⁴ One fundamental difference between these two methods of nitridation is the resulting nitrogen profile in the gate dielectric. In thermal nitridation the last part of the gate oxide is grown in a nitrogen-rich environment, hence the peak of the nitrogen is incorporated at the Si-SiO₂ interface. In plasma nitridation, the nitrogen is added from the top surface downward, so the peak concentration occurs at the polysilicon-SiO₂ interface. The results of Tan et al show that, not only does plasma-nitrided oxide have less NBTI shift, but they also associate this with the activation energy of the process. Authors from Toshiba reported on an intriguing phenomenon in which the oxide is damaged by charging (thereby exacerbating the NBTI threshold voltage shift), and then annealed by back-end-of-line (BEOL) processing such as the low-k curing process.¹⁵ Upon restress, these previously damaged and then annealed devices exhibit improved NBTI immunity relative to undamaged devices.

Scaled gate dielectrics

Several authors report data suggesting that oxides 2.0 nm and thinner (for conventional and nitrided oxides) are more immune to charging damage than thicker oxides, presumably due to their higher degree of leakage (Fig. 4).^16-18 This bodes well for the ability of modern dielectrics to withstand charging damage. Future dielectrics of equivalent thickness of <1.0 nm, however, are not likely to be composed of SiO₂, and will have different wearout mechanisms and reaction to damaging phenomena. Little is currently known about the reliability of such films, but the likely presence of defects and overcoordination of the bonding structure will probably provide lavish opportunities for instability.¹⁹ Tzeng et al report data on the degree of sensitivity to charging damage on two high-k films: Ta₂O₅ and Si₃N₄.²⁰ For a similar EOT (equivalent oxide thickness) of ;3.0 nm, they found the Ta₂O₅ to be more resistant to charging damage than Si₃N₄, and the physically thicker version of Ta₂O₅ to be less resilient than the thinner, speculating that bulk electron traps are responsible for the degraded behavior.

GATE OXIDE DAMAGE

4. Gate leakage data from three oxide thicknesses showing the most severe damage on the intermediate oxide thickness.

Conclusions and prognosis

Future work is likely to concentrate on low-k films in the BEOL, and high-k gate dielectrics in the front end of line (FEOL). There are many material properties to understand in these two major revolutionary shifts in the semiconductor industry. It is possible that the dominant form of damage may become more chemical than electrical in nature. Other possible future topics of interest may be related to an anticipated proliferation of analog and rf applications, where unique devices such as MIM (metal-insulator-metal) capacitors are built, and transistors may suffer degradation in unique modes, such as increased noise. There is no doubt that the industry will make progress on these and other fronts over the next months. Next year’s P2ID conference is expected to be held in Paris in April.

References

1. K. Cheung and C. Pai, IEEE Electron Dev. Lett., Vol. 16, 1995, p. 220.
2. M. Joshi, J. McVittie and K. Saraswat, "Development of a Physical Model of UV Induced Bulk Photoconduction in Silicon Dioxide and Application to Charging Damage," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, Maui, Hawaii, 2002, p. 23.
3. M. Okigawa, Y. Ishikawa, S. Kumagai and S. Samukawa, "Reduction of Ultra-Violet-Radiation Induced Damage and Its Time-Resolved Measurement Using Pulse-Time-Modulated Plasma," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 122.
4. C. Barlingay, R. Yach and W. Lukaszek, "Mechanism of Charge Induced Plasma Damage to EPROM Cells During Fabrication of Integrated Circuits," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 27.
5. J. Lauer, J. Shohet, C. Cismaru and R. Hansen, "Modification of Charge Produced During Plasma Exposure in Aluminum Oxide by Vacuum Ultraviolet Radiation," 6th International Symp. on Process- and Plasma-Induced Damage, Monterey, Calif., 2001, p. 68.
6. T.P. Ma, "Plasma Process Induced Radiation Effects in CMOS Technology," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 18.
7. S. Samukawa, K. Sakamoto, K. Ichiki, "High-Performance and Damage-Free Neutral Beam Etching," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 126.
8. S. Ma, et al, "Plasma Charging Damage Characterization of 200 mm and 300 mm Dielectric Etch Chambers Using Bias Voltage Diagnostic Cathodes," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 118.
9. T. Kikkawa, "Present Status and Future Trend of Low-k Dielectrics/Interconnect Technology for ULSI," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 154.
10. T. Yunogami, et al, "Development of the Damage Evolution Technology of a Low-k Film by Surface Voltage Technique," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 158.
11. N. Nakamura, et al, "Plasma Process Induced Wire-to-Wire Leakage Current for Low-k SiOC/Cu Damascene Structure," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 162.
12. B. Deal, et al, "Characteristics of the Surface State Charge (Qss) of Thermally Oxidized Silicon," J. Electrochem. Soc., Vol. 114, No. 3, 1967, p. 266.
13. D.Y. Lee, et al, " Process and Doping Species Dependence of Negative-Bias-Temperature Instability for P-Channel MOSFETs," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 150.
14. S.S. Tan, et al, "Negative-Bias-Temperature-Instability (NBTI) for p+-Gate pMOSFET with Ultra-Thin Plasma-Nitrided Gate Dielectrics," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 146.
15. N. Matsunaga, H. Yoshinari and H. Shibata, "NBTI Analysis of Antenna pMOSFET with Thermally Recovered Plasma-Induced Damage," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 142.
16. T. Hook, D. Harmon and W. Lai, "Gate Oxide Damage and Charging Characterization in a 0.13 µm, Triple Oxide (1.7/2.2/5/2 nm) Bulk Technology," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 10.
17. W.Y. Teo, et al, "Investigation on Dual Gate Oxide Charging Damage in a 0.13 µm Copper Damascene Technology," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 142.
18. G. Van den Bosch, "Evaluation Procedure for Fast and Realistic Assessment of Plasma Charging Damage in Thin Oxides," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 142.
19. A. Toriumi, "Reliability Perspective of High-k Gate Dielectrics <m> What Is Different From SiO₂?", Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 142.
20. P. Tzeng, Y.Y Cheng and K.S. Chiang-Liao, "Plasma Charging Effect on MOS Devices with Gate Dielectrics Using High Dielectric Constant Material," Proc. 7th International Symp. on Process- and Plasma-Induced Damage, p. 142.

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Author Information

Terence Hook is a senior technical staff member in IBM's Microelectronics division. He has been at IBM since 1980, when he received his Sc.B. from Brown University. During his employment at IBM he earned his Ph.D. from Yale University. He has worked on transistor design and process integration for bipolar, BiCMOS and CMOS technologies, and is now working on 90 nm CMOS technology development. He served as general chair of the 2002 P2ID conference.

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