Conductive AFM Reveals Oxide Breakdown Mechanism

With all the studies that have been done to examine thin gate dielectric breakdown (BD) and how it occurs, there is nonetheless an ongoing need to better characterize this breakdown phenomena due to the increasing influence on device reliability as transistors continue to scale.

In a recent study, researchers from the Universitat Autonoma de Barcelona (Bellaterra, Spain) have electrically imaged, for the first time, breakdown spots in standard MOS devices (silicon dioxide insulator with polysilicon gates) with two conductive atomic force microscopy (C-AFM) tools. The study provides insight into the local nature of oxide degradation, where initial breakdown affects an area that is a function of breakdown hardness and the applied current. With a simple modification to an AFM tool, the C-AFM provides a practical method for observing oxide breakdown. The researchers reported on their findings at the IEEE's 40th annual International Reliability Physics Symposium held in Dallas in May.

Dielectric breakdown proceeds as a three-step process — a wearout phase, the breakdown current runaway and, if the current through the structure is not externally controlled, thermal damage of the oxide. Thin oxides can exhibit hard and/or soft breakdown modes, and the area affected in breakdown is several orders of magnitude smaller than the total device area.

The researchers induced stress and breakdown in samples by using the AFM tip as the metal electrode in the MOS device. Fabricated from silicon with platinum/iridium or cobalt/chromium coatings, the conductive tips simultaneously and independently provide electrical and topographical information with a lateral resolution of ~10 nm (100 nm²) — the approximate order of magnitude of breakdown area.

Voltage is applied between the tip and substrate while current through the structure is measured. The research group used two AFM systems (from Digital Instruments and Nanotec), with picoamplifiers and analysis electronics. They studied MOS devices with poly-Si gates, thermal SiO₂ oxides (4.5 and 6 nm thick) grown on n-type substrates with device area of 6.2 ×10^-5 cm². The full devices allowed comparison with electrical tests using parametric analyzers and probe data. For the C-AFM measurements, the poly was stripped using a very selective etch using potassium hydroxide followed by DI rinse.

The range of data that can be gathered using a C-AFM is fairly extensive. It provides topographical images of the sample; two-dimensional current maps when scanning with a constant voltage between the tip and sample; and current-voltage (I-V) or current-time (I-t) characteristics at a given location on the oxide surface when applying a ramped voltage stress (RVS) or a constant voltage stress (CVS).

By comparing two AFMs with different set-ups — the first with current limited to 10 pA and 100 pA and the second with no current limit but measured to 300 pA — the group showed that, when no current limit is imposed during stress, larger areas are affected by the BD event. When a current limit is set, the current jump at BD is limited and, consequently, the BD path is kept from being completely developed.

The sequence of images at constant voltages (high and low) showed that current limit does not allow complete development of the BD path, leaving the oxide in a metastable configuration that lasts until the electrical environment is changed. The current jump through the initial BD area controls the total area affected by the BD. The researchers found that, although breakdown takes place in a very small area (~600 nm²), it laterally and quickly propagates to a larger area — from 1 × 10⁴ nm² to 1.6 × 10⁵ nm² in these tests. The BD spots then do not grow further. While some BD spots (in the saturation region) represent a very low resistive path, so that large currents can flow through them, others (at lower currents) still present some resistance to the current flow, supporting the observation of soft and hard breakdown events.

Another finding was that the dielectric strength of an oxide spot is influenced by nearby breakdown events. The observed distribution of dielectric strength, found by stressing different locations on the oxide, strongly depended on the distance between each measurement point, due to trapped change in the oxide. Therefore, assuming the area affected by the initial BD has a diameter of 450 nm, the estimated wearout area is ~1.6 × 10⁵ nm².

For additional information on yield management, go to www.semiconductor.net/yield.