Yield Improvement on Sub-0.18 µm DRAMs

A new self-aligned contact process for 0.15 µm DRAMs, developed by researchers at Infineon Technologies (Villach, Austria) and IBM Semiconductor Research and Development Center (Hopewell Junction, N.Y.), delivers significantly higher product yield than was obtained by scaling the 0.25 µm process.

For advanced trench capacitor DRAMs, the array contacts are borderless to both the isolation and the gate conductors. A new process using C₄F₈ -CH₂F₂ etch chemistry provides improved etch selectivity, allowing use of a thinner nitride gate cap, and smaller-aspect-ratio gate etch, BPSG fill and contact etch. Changing the contact shape from square-like to rectangular contacts improves the lithography process window by 40% and reduces the sensitivity to misalignment.

For the existing 0.25 µm DRAM process, a C₄F₈ -CO etch chemistry provided high-selectivity RIE of BPSG relative to the SiN cap. This chemistry provided high selectivity by forming polymer on the nitride but not on the BPSG. With device scaling to 0.175 µm, however, excessive polymer formation in the contact area led to RIE lag and etch stop before reaching the contact bottom (Figure ). Contact area became insufficient, especially in the case of any contact/gate misalignment, which produced higher contact resistance and possibly electrical opens.

BPSG etching using C4F8-CO chemistry, prior to SiN liner etch, shows incomplete etching of the contact due to excessive polymer formation (top). A change to rectangular-shaped contacts and C4F8-CH2F2 chemistry (bottom) enabled complete etch and access to the full.

The researchers used four-point probe, Kelvin structures to monitor the resistance of single contacts. Chains of 100K contacts with links to diffusion, bit line contacts, and first metal layers were used to monitor continuity. Array-like leakage structures monitored word line/bit line leakage. SEM and TEM analysis illustrated the results.

With the initial C₄F₈-CO chemistry, reducing the C₄F₈ flow rate did reduce RIE lag, but the etch still did not provide adequate polymer removal. Polymer formation could be limited by adding O₂, but the selectivity to SiN was poorer, leading to unacceptable nitride erosion (130 nm). However, the C₄F₈-CH₂F₂ chemistry offered much better selectivity, reducing nitride erosion to 40 nm. With this process, the nitride gate cap thickness could be reduced, which lowered the aspect ratio of the gate etch, BPSG fill and contact etch processes.

In terms of contact shape, the resistance of an aligned single contact is the same for square and rectangular contacts. However, the spread and distribution of contact resistance for a single contact (Kelvin probe structure) shifted to higher values for the square contacts. Monitoring of the out-current chain yield of chains with 100K self-aligned contacts showed significantly higher batch-to-batch yield, which could be explained by the reduced sensitivity to misalignment. Simulations showed that the 56% increase in contact area increases the lithography process window by >40%. The Infineon/IBM group showed that, by changing etch chemistry and switching to rectangular contacts, yield and process windows of the self-aligned DRAM contacts were substantially improved for sub-0.18 µm devices. For more information, see Rupp et al in the May 2002 issue of IEEE Transactions on Semiconductor Manufacturing.

For additional information on yield management, go to www.semiconductor.net/yield.