Electromigration No Problem for Nano Interconnects

A team in the Nano Processes department in the Research Labs of Infineon Technologies (Munich, Germany) has demonstrated that further shrinking of today´s state-of-the-art chip wiring will result in metal lines meeting electrical reliability requirements for chip manufacturing into the next decade. Infineon researchers, in conjunction with International SEMATECH (Austin, Texas), have successfully performed an electrical assessment of sub-70 nm copper lines down to a 40 nm linewidth. Metal lines as narrow as 55 nm will be used for the local interconnects in the generation of MPUs expected to be in production in 2010.

High current densities are the driving force for material transport in metallic wires (i.e. electromigration), which in turn degrades reliability and makes the wires prone to failure. Supreme electromigration resistance is a key requirement for chip metalization, and hence the key criterion for assessing the quality of the wiring scheme.

In the Infineon investigation, a mean-time-to-failure (MTTF) of passivated damascene sub-70 nm copper lines of 80-90 years was obtained, a value comparable with that for today´s products with 180 nm critical dimensions. The maximum current densities obtained by destructive testing (current ramping until burn-through) were in the 80-100 MA/cm² range (Figure). These maximum current densities are exceeding those known from today´s most advanced technologies by a factor of 2-5, and they are by more than an order of magnitude higher than the International Technology Roadmap for Semiconductors (ITRS) requirement for non-destructive maximum current densities (3.9 MA/cm²) in end-of-roadmap (2016) MPUs.

The location of failure in the test structure for almost all of the investigated samples was the same: the supply line to the test structure. Manfred Engelhardt of Infineon said he expects still higher values for both MTTF and maximum current density with an optimized design of the supply lines to the test structures used. "We used a test structure that was available at SEMATECH. We found that the feed line, in retrospect, was a problem. As a result of proximity effects in photolithography, we found some line narrowing at the transition where the feed line entered the test field. There was some current crunching, resulting in a high current density in that reduced cross section of the line."

1. Maximum current densities of nano interconnects (cross-sectional area below 0.05 µm2) obtained by destructive testing. The corresponding maximum current density data for cross-sectional areas exceeding 0.5 µm2 are taken from K.S.

2. Shown is a nanoscale damascene copper line that was driven to burn-through and failed right at the location where the sample line enters a test field with non-connected dummy lines. (Source: Infineon)

The obtained maximum current densities are only about one order of magnitude below the values reported for carbon nanotubes, which are known for their extremely high current-carrying capabilities resulting from their unique physical and chemical properties.

The structures were fabricated by use of standard deep ultraviolet (DUV) manufacturing lithography for pattern generation on a silicon-based hard mask, and subsequent narrowing of the hard mask opening by a removable spacer technique used for patterning of the intermetal dielectric. The silicon wafers were processed with today´s standard semiconductor manufacturing equipment and processes developed for 250 nm dimensions.

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