Single-Wafer, Short Cycle Time Wet Clean Technology
Steven Verhaverbeke, Satheesh Kuppurao, Christopher Beaudry and J. Kelly Truman, Applied Materials Inc., Santa Clara, Calif. -- Semiconductor International, 7/1/2002
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Wet chemical cleaning has been the workhorse in the semiconductor industry for more than 30 years. In 1965, Werner Kern and David Puotinen performed the first systematic study on the wet chemical cleaning of silicon surfaces, which was published in 1970.1 This approach proved to be so successful that the industry adopted it. Even now, after 30 years, so-called RCA cleaning — named after the company where Kern and Puotinen developed this process — is still widely used. Other cleaning processes recently have been proposed — the IMEC clean,2 Ohmi clean3 and DDC clean4 — but each of these processes had serious limitations and did not offer a substantial advantage over conventional RCA-type cleaning.
A typical RCA-type cleaning sequence consists of two steps. The first step, which is often referred to as the standard clean 1 or SC1, consists of an immersion in a bath of NH4OH/H2O2/H2O for ~10 min. This step is mainly aimed at removing particles and organic contamination. The second step, which is often referred to as standard clean 2 or SC2, uses a mixture of HCl/H2O2/H2O for ~10 min. This step primarily is aimed at removing metallic contamination, often deposited during the SC1 step.
In a typical 0.13 µm logic flow, there are about 54 cleaning steps in the front end of line (FEOL) and 45 cleaning steps in the back end of line (BEOL).5 This is illustrated in Figure 1 . The pre-diffusion cleans (20 steps) and the post-ash cleans (30 steps) typically include some variant of the RCA cleaning process. With smaller device geometries, the number of cleaning steps increases and is reaching >100 steps in some recent process flows. Increasing the number of cleaning cycles contributes to additional cycle time, cumulative silicon and oxide loss, and damage to fragile structures. Therefore, a shorter, more efficient cleaning process is critical to achieving high-productivity device manufacturing.
| Applied Materials’ 300 mm single-wafer Oasis Clean, with new chemistry and megasonics clean technology, removes virtually 100% of front and backside particles in <30 sec. |
Single-wafer thermal processing techniques increasingly have been adopted in favor of more traditional batch systems because of technical performance, ease of integration with other technologies, and a dramatic reduction in production cycle time that enables customers to bring products to market more quickly.
With the advent of 300 mm processing, batch wet clean systems pose increased risk of cross-contamination during critical cleans because of the decreased pitch between wafers and chemical recycling. Process constraints imposed by advanced devices (<0.13 µm) also restrict the amount of etching required by batch systems to obtain the high levels of particle removal and surface cleanliness. Single-wafer processing eliminates these hurdles and enables better technical performance for fine geometries. A single-wafer system also can reduce DI water consumption per wafer by an order of magnitude (10×) over batch systems.
One benefit of single-wafer wet processing is the potential to integrate it with complementary technologies. In the case of wet clean, its integration with gate dielectric deposition can control the surface condition for every wafer and reduce process variability. In addition, advanced gate dielectrics may require a variety of surface treatments under controlled conditions (e.g. ambient-controlled) that are possible only in a single-wafer mode. Also, integration of wet clean with dry photoresist-strip processes enables rapid turnaround and easy queue management in a fab, as well as reduced risk of particle growth between the strip and clean processes.
| 1. Typical wafer cleans required in a 0.13 µm CMOS process flow, with about 54 cleans required for just front-end processing. |
Production cycle time directly impacts a chipmaker's profitability. Since time-to-market is often critical, a single-wafer processing line enables more flexibility in lot scheduling and results in a faster cycle time and reduced work-in-process. Single-wafer processing also enables rapid prototyping and quicker development of new products.
Reducing the cycle time of the wet cleaning/etching step has a big impact on overall fab cycle time. In this paper, we will use the HF-SC1-SC2 dry cycle as a case study, but the results apply to most wet cleaning steps, which contain the RCA cycle or part thereof in some permutation. This step by itself is usually repeated up to 20× in some VLSI process flows. The same applies to other similar wet cleaning steps such as SPM-SC1-SC2 dry. Here we present a new process technology for wet cleaning that reduces the cycle time of a 1 hr process (DHF-SC1-SC2) to ~2 min. This implies that four wafers (or fewer) for this process can be completed in <2 min instead of >1 hr, and a full 25-wafer lot can take <15 min. In fabwide simulations, it has been shown that single-wafer processing applications can result in a >35% reduction in cycle time.
| 2. New approach reduces the cycle time of HF-SC1-SC2 from >1 hr to 2 min. |
In designing our new approach, we decided to build upon the conventional RCA chemistry (Fig. 2 ). To reduce cycle time, we shortened the dilute HF (DHF) etch from 5 min to <30 sec using a horizontal spin and dispense/spray concept that allows very short etch times with very good uniformity. High-concentration HF with very brief exposure times can be used in this approach; uniformities <1% (1σ) are achievable in a horizontal spin system, even with 15-20 sec etch times.
The traditional SC1-SC2 cycle, where each step takes ~10 min, can be reduced into a single step of 30 sec by using the following approach: The metal removal function of the SC2 can be combined into the SC1 by using a modified SC1 that includes chelating agents. The chelating agents take over the traditional metallic impurity removal function of the HCl, but work at high pH. Chelating agents in SC1 have been used before, such as the use of ethylenediaminetetraacetic acid (EDTA) in SC1 about 11 years ago.6
The SC1 process itself can be reduced from 10 min to 30 sec by using a much more efficient and novel full-coverage megasonics unit. In a conventional wet bench, the megasonics crystals typically are mounted on the bottom of the tank, and their energy is dispersed over 50-100 wafers. In a single-wafer horizontal spin solution, if the megasonics system is properly designed, the acoustic energy can be focused uniformly over a wafer, making it 50-100× more efficient.
| 3. Drawing of a four-chamber single-wafer, short cycle time wet clean system. |
The new cleaning approach incorporates a gentle, full-coverage, non-damaging megasonics unit that cleans more effectively and rapidly than existing technologies. Surfactants added to the SC1 avoid any redeposition of particles and help achieve a total process time of 30 sec. Drying relies mainly on centrifugal force (spin) to dry a wafer in 20 sec.
If we combine four horizontal spin chambers into a single system (Fig. 3 ), each chamber has a cycle time of 2 min for an HF-modified SC1 clean-dry cycle. Thus, a four-wafer lot can be processed in about 2 min. Such a system demonstrates a throughput of >100 wph, making it suitable for volume manufacturing.
Particle removal efficiencyThe addition of a surfactant to the SC1 solution greatly improves the particle removal ability of the SC1 chemical step. Surfactants increase a cleaning solution's effectiveness by helping it wet the wafer surface and dispersing (or carrying) particles from the wafer surface, all at very low concentrations. In addition, surfactants help suppress redeposition of very fine particles that are removed from the wafer surface (generally <0.14 µm) and ensure that fine particles stay in solution and can be easily rinsed later.
We investigated several types of surfactants and their ability to enhance the particle removal capability of our clean, concentrating mainly on anionic and non-ionic surfactants. A non-ionic surfactant that rinses from the wafer surface easily, leaves no residue, adds no organic or metallic contamination to the wafer surface, and is low foaming was selected. The surfactant also offers enhanced particle removal rates over a typical SC1, needs a low concentration to obtain critical micelle concentration (CMC) point and provides a high zeta potential.
We compared the Si3N4, Si and SiO2 particle removal efficiency of the traditional SC1 and our short- cycle clean in a single-wafer cleaner with novel megasonics for a 30 sec clean on 300 mm wafers. The results are shown in Figure 4 . It is clear that the traditional SC1 does quite well on SiO2 particles but has difficulty removing silicon particles. The surfactant added to the clean solves this deficiency. The SC1 clean removes only 90% of the silicon particles in 30 sec, whereas the modified SC1 clean (with surfactant) can remove up to 98% of these particles in 30 sec.
Though Si3N4 particles are easier to remove than Si particles, Si3N4 particles are commonly used as the standard test for particle removal efficiency. For Si3N4 particles, the standard SC1 delivers a removal efficiency of 95%, while the modified SC1 clean (with surfactant) achieves 99% removal efficiency in 30 sec.
Metallic impuritiesIn aqueous solutions such as SC1, a silicon wafer surface is hydroxide terminated. The interaction of the metal ions in solution and the silanol surface groups can be described by the following equation where Mx+ is the metallic ion:
-Si-O-H + Mx+ « -Si-O-M(x-1)+ + H+
| 4. Comparison of SC1 and short-cycle AM-Clean for SiO2, Si and Si3N4 particle removal efficiency. |
This equation is similar to the interaction of metal ions in solution with a weak acid ion exchange resin. We can see here that there are two ways to reduce metallic ions from depositing on the wafer surface.
The first is to increase the concentration of H+. This is done by the traditional SC2 solution. Acidifying the solution at the same time produces a solution in which most common metallic ions are soluble, provided that a suitable oxidizer, such as dissolved O2, H2O2 or O3, is present in the solution to prevent any reduction, especially of such metallic ions as Cu2+. However, this chemisorption/desorption equilibrium equation provides us with another mechanism for metallic impurity removal. If this is achieved by binding the free metal with a ligand so the combined complex remains soluble, we have created the same conditions for metallic impurity removal as the common SC2 solution. These ligands are often referred to as chelating, complexing or sequestering agents, one of the most popular being EDTA.
The advantage of this approach to metallic impurity removal is that the acid environment is no longer necessary. Metallic impurities can be removed from oxide surfaces at alkaline pH values using chelating agents, which are commonly used to remove particles such as the ubiquitous SC1 solution. This opens the door for an all-in-one universal cleaning solution, which is necessary to reduce cycle time when using single-wafer processing.
In our solution, we have used a chelating agent with a reduction in free ions of roughly 1035 for iron. We measured the metallic impurities after this clean to validate the combination of SC1-SC2 into a single step. The metallic impurities after this clean (Fig. 5 ) are below the VPD-ICPMS detection limit, which is on the order of 1E8 - 1E9 atoms/cm2.
| 5. Metallic impurity levels after the AM-Clean are at or below the VPD-ICPMS detection limits. |
As mentioned above, we selected chelating agents and surfactants that can be completely rinsed. First, we measured the characteristic peaks in a time-of-flight secondary ion mass spectrometry (TOFSIMS) spectrum of the chelating agent and the surfactant by depositing a concentrated solution on the wafer and drying it in a nitrogen environment. TOFSIMS measurement following a clean and rinse cycle did not exhibit either the chelating agent or surfactant characteristic peaks. Hence, even a short 20 sec rinse effectively removes all traces of chelating agent or surfactant. This has been further evidenced by the absence of any particles on wafer surfaces that might indicate surfactant residues.
Process validationOnce the basic performance characteristics were established, a 10-day, >5000 wafer marathon with the DHF-AM-Clean process was carried out to validate this concept in a production environment. Wafers were sampled periodically to monitor all the basic characteristics of this clean such as throughput, reliability, metallic contamination, organic contamination, water consumption, chemical consumption, particle adders on the front and backside, particle removal efficiency, oxide etch uniformity and repeatability. The two biggest challenges in terms of repeatability for any cleaning process are the excursions of particles and control of the etch rate, especially wafer to wafer.
The particle removal efficiency of the modified SC1 clean with megasonics exhibits virtually 100% particle removal from both the front and backside of the wafer. During this marathon we measured all particles >0.12 µm. The starting particle count was generally <50 for particles larger than 0.12 µm. The area counts are included in the particle counts. Almost 99% of the monitor wafers exhibited <15 particle adders with an average value of <2 adders during the entire run. The tight control over particle excursion during an extended period of use indicates the stability of single-wafer processing and its ability to meet production requirements for stringent cleans.
SummaryIn this paper, we have presented feasibility data for a new short-cycle wet clean (AM-Clean) using a single-wafer processing approach that offers excellent particle performance, oxide etch uniformity and metallic impurity performance. This clean combines the traditional SC1 and SC2 steps into one step by using the SC1 as the base and adding a chelating agent and surfactant to it. This allows the SC1 step to remove metals and particles in ~30 sec, when combined with an efficient megasonics set-up. Such short process times on a single-wafer platform enable high-throughput, fast-cycle-time processing that cannot be realized in batch systems. This clean meets or exceeds all regular performance metrics used to characterize cleaning, and has been proven production-worthy over an extended run.
| Author Information |
| Steven Verhaverbeke is technology manager for Applied Materials ' Wet Clean Division (Materials Transistor and Capacitor Group), focusing on development of new wet cleaning concepts and processes. He received his Ph.D. in applied sciences from Katholieke University. |
| Satheesh Kuppurao is marketing manager and strategic technologist for Applied's Wet Clean Division. He has a Ph.D. in materials science from the University of Minnesota and B. Tech from the Indian Institute of Technology. |
| Christopher Beaudry is a member of the technical staff for Applied's Wet Clean Division. He received a Ph.D. in ceramic science and engineering from Rutgers University. |
| J. Kelly Truman is general manager of Applied's Wet Clean Division. He received a B.S. in metallurgical engineering and materials science from the University of Notre Dame, and M.S. and Ph.D. degrees in materials science and engineering from the University of Florida. |
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