Exploring Advanced Interconnect Reliability

The reliability behavior of copper/dielectric interconnects in dual-damascene structures is significantly different from that experienced with aluminum/oxide interconnects, largely due to the geometrical differences in fabrication scheme. The primary cause of aluminum electromigration (EM) was grain boundary diffusion. By patterning aluminum lines over redundant TiN/Ti layers, the design allowed electrical continuity even after aluminum line depletion from EM damage.

With copper, known for its better EM performance, EM is primarily driven by interface diffusion, but also surface diffusion. Grain boundary and lattice diffusion still occur, but they are lesser contributors.¹ "What is driving so many reliability studies is that everyone expected significantly better electromigration performance with copper, and with the current copper integration schemes we're just not seeing that today," said Sanjiv Mittal, vice president of the modules business group for Applied Materials (Santa Clara, Calif.).

Copper interconnects also suffer from stress-induced voiding. Repeated cycling to ~400°C to room temperature causes residual film stress that can lead to stress migration failures. Low-k materials have higher coefficients of thermal expansion (CTE) than oxides, making stress management in the stack more challenging. CTE differences also impact packaging.

Copper interconnects exhibit bimodal failures — with the early failures dominated by void formation at the via bottom interface and late (strong) failures the result of voiding in the trench. The weak mode relates directly to the Cu/Ta interface quality.

1. In copper dual-damascene interconnects, the failures tend to occur at film interfaces and can be due to insufficient cleans, poor adhesion with dielectric films or metal barrier discontinuity. (Source: Novellus)

Once the numerous chip-level copper/low-k integration problems are worked through, the greatest challenges lie in obtaining production-worthy, high-yielding devices that can be packaged and pass standard reliability testing.

In the past two years, assembly and packaging challenges for copper/low-k devices have come to the forefront, including the stack's ability to endure dicing, wire bonding and flip-chip assembly. Michelle Rasco, Motorola assignee to International SEMATECH (Austin, Texas), and coworkers recently assessed the viability of copper/low-k devices passing flip-chip, aluminum wedge bond and gold ball bonding assembly. "Though the industry is trending toward flip-chip for advanced devices, significant volumes may still be produced with more traditional methods," she said.² Aluminum wedge bonding stressed the die the most. The study revealed high yields and electrical test results were possible using an ultralow-k material (JSR's LKD 5109). However, in some cases it was necessary to use thicker passivation and an additional oxide layer on top of the structure to deliver a more mechanically stable stack.

2. Via chain resistance of 130 nm lines/spaces gives a strong indication of process stability. (Source: IMEC)

The need to assess packaging compatibility with low-k materials presents a significant change to on-chip process development. "A serious problem, in terms of mature structures, is that everybody's package is a little different," said Mike Armacost, director of the low-k damascene business unit at Applied Materials. "There are JEDEC testing standards that we are using, but it's hard to solve the problems for every case."

"People were surprised by how severe the integration and packaging issues were, especially for the softer materials, which has caused a delay in adopting low-k materials," said Chris Werkhoven of ASM International (Bilthoven, Netherlands). He said that three parameters have become central to a film's ability to be processed in a multi-level metal, dual-damascene process: hardness, elastic modulus and cohesive strength, as published recently by Intel.⁴ "It is a combination of process chemistry and process conditions such as temperature, pressure, residence time of the molecules in the plasma and the plasma characteristics themselves that contribute to the specific chemical structure of the film, its hardness and reliability performance," he said.

The industry has also been delayed by the need to identify a feasible roadmap for reducing the ILD's k value from 2.8 to 2.4 to 2.2 and below. "People want to see 300 mm wafers with an acceptable k=2.4 process," Werkhoven said. "If you cannot demonstrate 2.4 with 300 mm wafers at this time, the chances that you get any business, even for 2.8, is minimal."

The biggest reliability issues are the result of voids in the copper. Studies have shown that voids can be the result of stress migration or EM, and can be caused by many different sources of defectivity — from CMP and copper fill to poor adhesion between copper lines and the cap, for instance. For the most part, reliability issues relate directly to the copper interconnect and barrier metal interface, but the interfaces with low-k dielectrics and dielectric barrier films tend to exacerbate any existing problems with the copper process (Fig. 1).

3. The deposited copper barrier was unable to cover in the nitride recessed area, which was undercut during barrier open. This caused reliability failure after thermal cycling (above). Modifications to the barrier open step fixed the problem (below). (Source: Novellus)

Copper voids form for a number of reasons, but thermal cycling causes voids to coalesce and migrate to the via bottom. Even though problems such as voiding, copper hillocking and microbridging are often detected after copper CMP, the root of the problem can be a process other than CMP, explained Bob Fiordalice, senior director of strategic alliances at KLA-Tencor (San Jose). For instance, voiding is typically related to the quality of the thin barrier metal (most often TaN/Ta) surrounding the copper lines and vias. Via chain resistance measurements are important to process evaluation (Fig. 2), but there is also a strong need to identify the exact location of open or resistive vias among the millions of vias on a chip (see "Via Chain Monitoring in Copper Interconnects ").

Voids tend to form in vias first. This is primarily due to the large aspect ratio difference between the via and line dimensions. While the thicker trench lines have very high current-carrying capability, the vias are challenged to carry such high currents with continued downscaling. "Improving the current density that these interconnects can carry is going to be an important issue going forward," said Chris Ngai, product manager of the process modules business group at Applied Materials.

To improve via resistance and reliability performance, many device manufacturers are reducing the barrier thickness at the via bottom, while still trying to maintain barrier coverage on the feature sidewalls. Ultimately, this approach will allow the best connectivity, but in the case of unlanded vias, the barrier coverage would not be sufficient.

With each new technology generation, the barrier must be made thinner. Before the 65 nm node, however, device manufacturers may change barrier material and method from PVD TaN/Ta to CVD of, most likely, TiSiN. TiSiN can offer better long-term reliability than tantalum, but it may have drawbacks such as poorer adhesion to low-k dielectrics and harder-to-get good copper wetting.

"The copper voiding issues observed post-ECD anneal are primarily the result of an interaction between the patterning and metalization," said Jeff Wetzel, process technology manager of the U.S. technology group at Tokyo Electron America (Austin). "It's a complicated issue to work through because voiding at the copper interface with the barrier film can be due to an adhesion problem, but it could also point to a copper fill problem or the barrier influencing the conformality of the copper seed," he said.

"Many defect phenomena are detected at post-CMP inspection, such as copper corrosion, metal, organic or slurry (alumina) residue, which can lead to line shortening," Fiordalice said. Residue removal is particularly complicated by low-k dielectrics because less aggressive chemistries must be used.

4. A particularly important interface lies between the copper and nitride cap. If not properly integrated, a copper silicide layer can form. A best known method (BKM) for this FSG/copper process fully removes the copper oxide and other residues prior to nitride capping. (Source: Applied Materials)

In addition, because CMP is such a costly process and many defects can result, device manufacturers often choose to perform FIB cross-sectioning and inspect the wafers fully before CMP, according to Janet Teshima of FEI Co. (Hillsboro, Ore.). Inspection feedback and feedforward are very important to monitor plating performance, she said. "We also see a fair amount of inspection after via and trench etch, especially looking at uniformity across the wafer." Teshima said a cross section on a back-end process, given the coordinates from an inspection tool, takes ~5-10 min.

Control of the metal barrier's interface with the underlying metal line is crucial: It depends on a well-controlled dielectric etch process, complete residue removal (which can include organic materials, metals, silicon and fluorine compounds), conformal barrier coverage, excellent sidewall adhesion, and a controlled barrier open step. Next, the copper is deposited by plating in a bottom-up fill, the copper is annealed, followed by CMP and copper capping, usually with SiN.

Victoria Shannon, vice president of Integration and Applications, Novellus Systems (San Jose) summarized many of the causes of EM and stress migration failures. "Our advanced barrier metals group is looking closely at the pre-treatment for the copper diffusion barrier," she said. "This turns out to be one of the key areas for electromigration and line-to-line leakage."

The barrier open etch is also key (Fig. 3). "When you perform the barrier open etch, you have to be sure that you don't undercut the film and create defects. PVD has a hard time covering an undercut feature," Shannon said. Novellus uses a low-temperature process for barrier layer deposition to reduce the likelihood that copper from the underlying metal line extrudes up into the via due to the CTE mismatch at elevated temperatures.

Adhesion of the various layers in the stack is key; otherwise the stack may not survive CMP. And CMP tear-out is not just an issue at the wafer edge, but across the entire wafer. During CMP, insufficient slurry between the pad and wafer can cause delamination. Delamination issues have also caused some CMP suppliers to provide processes for low-downforce CMP. However, with this approach comes a significant hit in throughput. Next, the wafers undergo annealing to form the proper copper grain structure.

Once wafers have undergone CMP and annealing, the copper is capped, typically with SiN. This interface is very important to reliability. Prior to cap deposition, all copper oxide must be reduced and the substrate prepared for the best adhesion (Fig. 4). Various plasma treatments are used to best remove copper oxide and increase adhesion to the cap. The SiN deposition (or SiC) is also performed at high temperature, a step that can cause hillocks in the copper if not controlled properly. "Because stress gradients in the metalization scheme can cause hillocking, the balance between the various thermal processes involved is critical," Fiordalice emphasized. In addition, the concern over copper corrosion tends to limit the lag time between CMP and cap layer deposition.

Because the various interfaces between dielectrics, copper and barriers are so tied to reliability, any elimination of layers becomes advantageous. Also, since many of these films are SiN (k=7-9), low-k requirements call for their removal. Over the past year, many device manufacturers have eliminated the intermediate etch stop (SiN- or SiC-based) between the trench and via. "Taking out the dielectric diffusion barrier at the bottom of the via is going to be quite a bit more challenging," Shannon said.