San Jose Kicks Off SEMICON West

Like the poor kid in the classroom whose last name starts with Z, San Jose is finally getting its shot at being called first in this year's SEMICON West roll call. In their sixth year of being divided between front- and back-end processes, the exhibits will lead off for the first time with the back end, opening in San Jose, then moving up to San Francisco the next week for the front end. This arrangement is just for this year, however, as SEMI plans to return the event to its front-to-back format in 2003.

Assembly, packaging and test will be presented Wednesday, July 17 through Friday, July 19 at the San Jose Convention Center, split among several halls. Exhibition hours are 10 a.m. to 6 p.m. July 17 and 18, and 10 a.m. to 4 p.m. July 19. Registration details can be found on SEMI's Web site (www.semi.org/semiconwest).

At this year's SEMICON West, there is sure to be a strong focus on advanced packaging technologies, including wafer-level packaging (WLP), wafer bumping, flip-chip and chip-scale packaging (CSP).

1. This year, the first stop for those attending both ends of SEMICON West will be in San Jose. (Source: San Jose Convention and Visitors Bureau)

Wafer bumping involves the deposition of under-bump metalization (UBM) by sputtering, which can require three different metals, such as Al-NiV-Cu. This is followed by deposition, exposure and development of a relatively thick layer of photoresist (80-100 µm), descum, electroplating, resist strip, UBM etch and, finally, reflow.

Equipment and materials that address the need for redistribution lines (RDL) will also be a focus of this year's show. RDL is an additional level of wiring that repositions I/O pads from the perimeter to alternative locations on the chip. A redistribution process is necessary if perimeter pads have to be rerouted into another I/O layout. This is necessary if the perimeter pad pitch is too fine for the PCB, for example, or — more generally — if the pad layout on the die does not match the layout of the PCB. In many cases, perimeter pads are rerouted into area arrays.

The traces of the redistribution layer are embedded into an isolating/dielectric material. Examples of this dielectric material are BCB or polyimide. Today, photosensitive dielectrics are often used to minimize the number of process steps. Both BCB and polyimides are available with photo-patternable formulations. The process steps depend on whether the redistribution traces are aluminum or copper. For aluminum traces, the aluminum is sputtered onto the wafer and the traces are etched using a lithography-defined etch mask. In case of copper traces the metal is electroplated.

Two seminars will be held on these kinds of technologies: The Advanced Packaging & Interconnect Alliance (APiA) will host a seminar July 18 in San Jose, and the Semiconductor Equipment Consortium for Advanced Packaging (SECAP) will host a WLP seminar July 23 in San Francisco.

Of course, the back end also brings with it the latest test technologies and issues. Typically, during the final stages of manufacturing, each die on a wafer is probed to see if it's working properly, since there's no sense in packaging a defective die. This procedure — often called "wafer sort" — requires a probe card that has pins that touch down on the bonding pads of the die; a probe system to move the wafer under the probe card; and an automatic test system to provide the signals that test the functionality of the device.

2. For the sixth year running, the San Jose Convention Center will host exhibits for back-end processes. (Source: San Jose Convention and Visitors Bureau)

After packaging, the device typically goes through a thermal cycling "burn-in" procedure that weeds out early failures. Finally, the functionality and speed of the device is tested and the devices are sorted or "binned" by speed (faster chips are naturally worth more). This requires an automatic test "handler" that inserts each device into a "test head" connected to automatic test equipment (ATE).

At SEMICON West this year, expect to see new developments in the equipment used for all these processes: probe cards, wafer probers, die bonders, wire bonders, wafer bumping, encapsulation equipment, underfill, burn-in, handlers and ATE (as well as the inspection tools needed to make sure that, for example, wafer bumps are nice and round and located where they are supposed to be). It's especially interesting to note the developments in ATE, which must keep up with the trend to faster chips with higher I/Os and more functionality (i.e., the system on a chip). There is also a push to better integrate the data that is acquired at the wafer sort stage — probe yield data — with the manufacturing defects that led to the yield loss.

In addition to the exhibits, SEMICON West's back-end lineup will include several technical and business programs (Table 1), including the SEMI Technology Symposium (STS), appearing at the show for the second year and covering a wide range of packaging, interconnect and manufacturing issues (Table 2).

Business presentations this year include Semiconductor Account Selling for "Non-Sales" Team Members, taught July 19 and 20 by Len Given of The Quest Team Inc., and Charles Smith of Action Pro Tem. The two-day workshop is designed to give engineering, marketing, and field service personnel and managers a better understanding of the sales process.

Touching on one of this year's hottest topics, Exporting to China — U.S. Government Resources will be presented Friday morning by Assistant Secretary of Commerce for Trade Development Linda Conlin, and representatives from the U.S. Foreign Commercial Service China and the U.S. Export Assistance Center. This is a free presentation, but registration is encouraged.

Of course, San Jose's special position this year in kicking off SEMICON West wouldn't be complete without the opening ceremony. This is planned for Wednesday, July 17, 9:30-10 a.m. at the San Jose Convention Center. SEMI President Stanley T. Myers will welcome exhibitors and attendees to SEMICON West 2002, and will present SEMI's board of directors.