Front-End Trends: Exhibitor Outlook

What will be the "buzz" at this year's SEMICON West? The pending upturn is sure to be the main topic of discussion, followed by news of developments in 300 mm, copper and low-k, wafer bumping and other technologies. Business in China, Taiwan, Japan, the United States and Europe also will be hot topics, as well as how long the industry can continue to stay on the path predicted by Moore's Law and the International Technology Roadmap for Semiconductors (ITRS). For insight on these and other topics, Semiconductor International asked some of today's leading CEOs and industry executives to give us their outlook on what they're expecting to see at SEMICON West 2002.

Advanced Energy Industries Inc.
Douglas S. Schatz
Chairman, CEO and President

E-manufacturing is similar to looking at a mountain in clear desert air — it's easy to see the mountain, but difficult to estimate the distance. Of course, e-manufacturing is a convenient way to label everything imaginable that could be done (in our own interest), "if only." Clearly, there is a compelling opportunity for our industry to improve both effectiveness and efficiency, and we are all frustrated with the progress. SEMICON West this year will bring more integrated products and technologies from major suppliers and partnerships touting the ability to solve real problems. We believe that this indicates momentum — that for the first time, we really are on the threshold of unlocking much of the available value. We believe that the reason for the delay has been the unavailability of the required information technology pieces — until now. The pieces are the four technical layers that are simultaneously required before the value can be unlocked. They include connectivity, data management, applications and domain knowledge. Connectivity brings access to the things in the tool — the sensors, subsystems, etc. Data management brings security, storage, compression and database operations. Applications bring analysis tools and a way to embed each user's intellectual property (IP). The pieces are here; applying our domain knowledge to develop "killer applications" will make it all come together.

The semiconductor industry's constant need to increase device speed and performance — traditionally accomplished through transistor scaling — has driven the development of new low-k materials. Now it is the interconnect of these transistors that limits device speed. This is due to the increasing resistance capacitance (RC) delay as the interconnect wiring is scaled. While changing from aluminum to copper wiring decreases the resistance of the interconnect, lower dielectric constant materials are required to decrease capacitance to minimize crosstalk and power dissipation.

Semiconductor manufacturers will either utilize chemical vapor deposition (CVD) or spin-on deposition (SOD) processes to create the required low-k layer. In the quest to develop the next low-k dielectric standard, most low-k SOD efforts have focused more on the basic material or blanket film than on the customer's bigger-picture needs. While properties of blanket films are important, they are of little consequence if the device manufacturer cannot produce the film in a short enough period of time, integrate the film into a semiconductor device, achieve integration yields in line with expectations, and extend the use of the film material to future device generations.

Air Products, working closely with a major semiconductor OEM, is readying an SOD offering for 100 nm devices called MesoELK. The product displays outstanding blanket film properties while also addressing broader customer challenges (process time of <5 min, successful integration in a damascene structure, excellent yields and extendibility of the material to future device nodes).

Low-k interlevel dielectrics (ILDs) are a dynamic, fast-moving application. As the semiconductor industry works to achieve lower k values for ILDs, each node on the silicon roadmap will require different materials solutions. Air Products is committed to providing the industry with the broadest, global materials portfolio.

To maximize the precision, repeatability and productivity of today's process tools, we will see a focus on integration, both in within-system and system-to-system capabilities, at this year's SEMICON West.

A new generation of metrology and inspection technologies is being integrated onto processing systems to provide virtually real-time, wafer-to-wafer process inspection. By integrating this function within the process tool, every wafer can be monitored to achieve better process control, rapid defect detection and faster corrective action without affecting wafer cycle time. The overall benefits are better equipment performance, higher yield and less scrap.

Monitoring technologies for etch and chemical mechanical planarization (CMP) systems have advanced to cover endpoint detection, film thickness measurement and wafer topography analysis methods that can stop or change the process with the precision of a few nanometers. Deposition systems also are beginning to use uniformity measurement for real-time excursion detection. Other emerging integrated metrology and inspection techniques being implemented on process equipment include CD metrology, defect material analysis and plasma monitoring.

Integrated tools can be used to feed information within a processing sequence to optimize process control and maintain in-spec tool performance. Multi-system control can significantly tighten operating parameters to achieve less chip variation, improving bin sort yield.

Today, a system that can be readily integrated with other systems in the fab is key to achieving the advanced levels of process control required to maximize yield of very complex devices while speeding time-to-production and time-to-market for new chip technologies.

We see two major, rapidly evolving trends occurring in the microelectronic materials industry today. While the materials market shift from North America and Europe to Asia is no surprise, the rate of market shift has been accelerated. We believe this is due to the increased fab capacity that is rapidly becoming available in China; the closure of the older technology and less-efficient fabs in North America and Europe; and the shift of production from OEMs to the Asian foundries, where a significant amount of semiconductor capacity has become available. Successful microelectronic materials suppliers must have a global business enterprise that includes an established Asian sales and distribution network, and a manufacturing and supply management infrastructure capable of supplying best-quality product at the lowest delivered cost.

The shift toward copper technology is also well known. However, market timing and technology choice continue to be big questions. Microelectronic materials suppliers are placing big bets. We are aggressively investing in both spin-on and CVD-based copper technologies, as device integration issues are slowing the copper commercialization process and shifting roadmaps to later dates. A key ingredient to success will be to work closely with customers to bridge the integration gap by offering an interconnected set of advanced copper technologies. This is causing the microelectronic materials suppliers to broaden their product lines and integrate these technologies at early development stages. Aggressive advanced technology development with our customers and joint-venture partnerships are the keystone to growing our global business.

At the 130 nm technology node and below, small variations in junction formation processes now make a significant and critical impact on drive current and off-state leakage. At the same time, rapid thermal anneal (RTA) processes such as spike anneals are operating near their control limits. To maintain yield of advanced devices, in-line pre- and post-anneal metrology increasingly is required.

Cost reduction of ultrashallow junction (USJ) processing is an additional driver for in-line process control for the implant and anneal module. Replacing traditional off-line destructive monitoring schemes with in-line approaches reduces the expense of test wafers. Measurements are possible at the module, saving time-to-detection and reducing work-in-process (WIP) affected by process excursions. Dramatic savings in qualification cycle time and development ramp time duration can be realized by in-line feedback — especially cross-wafer uniformity of 300 mm wafers.

Implant and RTA continue to be the dominant method for doping. However, concerns about extensibility below 70 nm drive increased R&D in advanced doping methods such as selective epi, laser annealing and solid-phase epitaxy. This creates the demand for extensible metrology such as in-line carrier illumination techniques — identified in the latest International Technology Roadmap for Semiconductors (ITRS) — that can meet both today's needs and those of advanced processes.

The transition to 300 mm has been significantly slowed by the weak economy of this past year. One of the crucial aspects of this transition will be tool vendors' ability to successfully integrate their equipment in the fab, allowing them to realize sales revenue. Even with SEMI standards in place, communication continues to be a challenge. Homegrown or legacy software has proven to be difficult and time-consuming to integrate. Our experience has been that, when equipment makers support the SEMI standards with modern software architectures, this process becomes easier. This has caused more companies to look to third-party communication vendors providing advanced software platforms that link the tool to the fab.

Communication software provides the necessary conduit out of the tool, enabling the eventual goal of e-diagnostics. With the introduction of new communication languages and process monitoring tools, the software must be able to provide multiple communication lines out of the tool. This will be the next standard demanded by the industry: a flexible software package that addresses all 300 mm communication challenges and is able to change as standards are updated. This will provide the necessary lines of communication to effectively utilize the information being produced by the tool.

Inventories have declined, utilization is rising, book-to-bill ratios are higher. All signs are pointing to a recovery. However, the global economy is still relatively weak, and no obvious technology is emerging as the leader of the recovery. Will this upturn be the start of a more sustainable, uniform period of growth, as some industry analysts have suggested? After the most abrupt decline in industry history, stable market behavior and durability seem unlikely. Without a clear driver for recovery, the current optimism may be short-lived. Worldwide capacity seems more than sufficient to meet and exceed demand, so the current upturn looks more like a self-fulfilling prophecy than the next boom. An important question at SEMICON West this year is, "Why are manufacturers buying capital equipment?"

The evolution of low-k dielectrics will be a very hot topic this summer, and the talk at SEMICON West will likely reflect this. Our guess is that discussions will move past individual materials and deposition methods, and on to the more important questions of what the finished dielectric stack looks like, whether it provides true low-k capability under real-world conditions, and what its cost of ownership (CoO) is. We at Dow certainly feel that SiLK resin, porous SiLK resin and the Ensemble product line, in conjunction with the equipment, materials and process capabilities provided by SiLKnet Alliance, present strong answers. But the important point is that, when these types of discussions start happening and clear answers emerge, it will be a sign that the low-k market is reaching a new level of maturity, which will enable it to be of true service to the semiconductor industry.

The impact of the high cost of advanced photomask sets on various semiconductor business models will be a hot topic at SEMICON West again this year. At design rules of 130 nm and below, optical lithography becomes more complex. To meet these challenges, mask users increasingly employ reticle enhancement technologies such as phase-shift masks and optical proximity correction (OPC). These technologies, along with increasing write and inspection times on expensive tools and the need for additional investment in R&D, are driving up the cost of mask sets.

Despite the value in every advanced photomask set, chipmakers — ranging from high-performance, high-volume producers to low-volume producers — are finding it difficult to absorb these costs. To mitigate this situation, the industry will need to abandon its one-process-fits-all approach to photomask production. Now more than ever, device designs vary by customer, end-use application, process and mask layer. DuPont Photomasks is working with customers to shift the focus away from specific mask tool platforms to image on wafer, and deliver mask set solutions that balance cycle time, price and performance based on each customer's exact device requirements.

IC manufacturers have realized that the ongoing adjustment to new, more complex products and manufacturing processes is a constant challenge to profitability. To succeed, they must create highly flexible, responsive and cohesive manufacturing operations that meet customers' expectations. For these companies, time to money after the introduction of new products or manufacturing processes can be dramatically compressed by optimizing manufacturing processes to reduce waste and inefficiency and improve product yield.

I believe that this year's SEMICON West will see a sharp increase in the range of software products offered, as chip manufacturers increasingly turn to software as the answer to improving efficiency and reducing costs. Industry analysts are predicting that the merchant semiconductor software market will grow from $350M last year to $1.2B in 2004-2005. This trend is driven by the competitive nature of semiconductor manufacturing, the need for chipmakers to develop and deploy global processes quickly, and the requirement to collect, analyze and act upon data quickly, efficiently and accurately from diverse sources.

For effective process management, equipment and process information must be shared throughout the fab and across the chipmaker's global organization. Until now, a lack of connectivity has prevented this from happening. Specifically, there has been a disconnect between equipment and processes, the plant floor and external systems, and the overall company with its partners. Ultimately, the corrective action needed to improve yield is not communicated in a timely manner across the manufacturing floor and across the enterprise. To meet this need, Electroglas launched the EGsoft Division to develop and integrate a suite of products that achieves Internet and intranet connectivity and allows true collaborative process management. The result is a cohesive software infrastructure capable of providing semiconductor makers with "actionable" information anywhere, anytime.

The promise of e-manufacturing is grand, but the challenges of achieving it are equally massive. Now that 300 mm manufacturing is clearly on the horizon for much of the industry, talk at this year's SEMICON West will likely include serious discussions on how we build a viable infrastructure that will enable the new levels of automation and productivity we seek.

Traditionally, capital equipment suppliers have relied on hardware differentiation to help customers achieve greater manufacturing yields and efficiencies. Chipmakers, in turn, coupled the hardware with fab-centric automation and data management software to improve overall factory efficiencies.

As we know, chipmakers today want more value from tool suppliers, which are being asked to take on more responsibility for overall manufacturing improvements. This can't be done with hardware alone. What's needed is a software infrastructure that will allow equipment suppliers to deliver those manufacturing improvements with smart combinations of hardware and tool-centric software.

Changes in SECS/GEM communications are a classic example. Although SECS/GEM is standards-based, it was clear early on that capital equipment suppliers needed focused, tool-centric solutions to meet their customers' requirements for this automation infrastructure. Looking ahead, the tool-centric approach will become more invaluable — especially in data visualization, data analysis, fault detection and fault classification applications — as equipment suppliers become increasingly responsible for the success of the e-manufacturing revolution.

Besides the sense that the worst may be over, this year's SEMICON West should highlight some key challenges: nanoscale and atomic-scale technologies, integrated process solutions and new metrology and process control schema.

Semiconductor devices and processes are in the forefront of nanotechnology. Deployment of new technologies that enable smaller geometries, more complex device structures and new materials has underscored the need to integrate process solutions that provide real-time information about device geometries, structures and materials for tighter process, defect and structural integrity controls.

These solutions include multiple processing systems extending beyond traditional boundaries. New measurement technologies and software that go beyond the conventional measurement and process control schema are now necessary to detect defects, perform instant root-cause analysis, and provide real-time feedback and feed forward of the information. These tools enable manufacturers to analyze buried defects, complex structures and multiple device layers and the interactions between these layers, increasing yields and optimizing costs.

All of this requires increased collaboration between equipment and materials suppliers and an increased need for software that delivers greater performance and value. These are significant challenges for our competitive industry, but we must face them and deliver real econometric value to our customers.

At SEMICON West 2002, we expect to hear discussion about a number of technology trends, all of which include an underlying message — the ongoing business challenge to improve our customers' capital productivity.

To be engaged at today's technology node and capable of advancing customers to the next technology nodes, a supplier must have "advanced process capabilities." That is, one's technology position must do three things. One, enable increased throughput or decreased cycle time as production demands evolve. Two, reduce the consumption of resources (footprint and consumables) on a continual basis. Three, it must include advanced process control (APC) elements to deliver run-to-run process consistency, fault detection, classification and, ultimately, process correction through integrated metrology and behavioral models. With these capabilities in place, customers will see a positive impact to their capital productivity for many years.

At this year's show the general trend in the semiconductor industry of companies moving up the food chain will become much more obvious. In the past few years, capital equipment makers have taken over significant responsibility for developing processes for their customers. This year we'll see that component and subsystems suppliers are beginning to follow suit by developing a tool infrastructure that will enable toolmakers (OEMs) to move up the value chain in turn.

In response to this need for more fully integrated subsystems, MKS has spent the past few years acquiring new technologies that can be designed and integrated into high-value products for customers. Each acquisition has been strategic to our mission to "surround the process chamber" and provide process infrastructure products and technologies that improve productivity. For example, MKS' recent acquisition of Tenta and IPC allows us to offer customers not only critical, computer-based process controllers, but also products that enable e-diagnostics and APC. These new MKS products can be integrated with our digital network products to provide a more complete process control solution. This solution, particularly useful in 300 mm tools, is an example of a technology that once was developed by the equipment makers, but is now being outsourced to the subsystem providers. This more complete infrastructure frees OEMs to focus on efforts in their own areas of core competence and trust that the outsourcing will be done and supported worldwide.

One trend that will begin to gain momentum this year is an increasing interest in direct write pattern generation for prototyping and small-volume production. This topic is stimulating interest because of the increasing costs of photomasks.

A mask set for the 90 nm node is expected to cost as much as $1M-$2M. Although innovative laser pattern generation may slow the acceleration of the cost increase, pattern generation, being the largest individual cost in maskmaking, composes no more than 25-40% of the total mask cost. Million-dollar (and more) mask sets risk eliminating many designs from being put on silicon, or even being moved from idea to the design board.

In the long run, such an evolution may put a significant number of businesses at risk. It is likely that, despite strong industry efforts, mask-set costs will continue to increase, and thus a complementing capability will be needed.

As a result, the industry is warming up to the idea of direct write. Although many challenges to this technology remain, the concept is beginning to appear economically viable for the first time because of spiraling mask costs.

In the past, metrology often has been viewed as a necessary evil of process development that lacks real value, and should be quickly minimized for volume manufacturing. This view is rapidly changing. APC is playing a more critical role with chipmakers, who in turn are placing increasing pressures on tool manufacturers to provide fully integrated process control and metrology solutions, especially as volume 300 mm production begins. Widespread APC adoption is also driven by shrinking feature sizes and the need for very tight process tolerances. Through the benefits of integrated metrology, APC provides predictability, increases productivity and helps achieve tighter manufacturing processes, all of which ultimately increase yield and profits. Integrated metrology enables real-time process control. As the adoption of APC continues throughout the industry, it's clear that integrated metrology is providing significant value.

This year at SEMICON West, as the equipment industry spins out of the downturn, its customers will be looking for solutions for the 65 nm process generation. Scheduled production on this node is a short 21/2 years away, yet many lithography issues remain unsolved.

Many experts expected 157 nm lithography or alternative, non-optical lithography solutions to fill in the wavelength gap for this generation. However, they remain unavailable. As a result, the feature sizes on this process generation are substantially smaller than the wavelength of the available 193 nm lithography equipment. Not only do transistors represent less than one-fifth of the wavelength, but the poly-interconnect represents only one-third of this wavelength — moving the subwavelength challenge further into this chip. Confronting this complex problem with manufacturable and cost-effective solutions is likely to dominate the show conversation. Subwavelength lithography-enabling solutions, such as phase-shifting technology or advanced OPC techniques, will undoubtedly preoccupy the minds and conversations of vendors and visitors.

In the past few months we've seen the first tentative signs of an IC industry turnaround, and semiconductor makers are rushing to ready new generations of innovative designs. However, chipmakers will face daunting challenges including the move to deep submicron technologies — 0.13 µm and below — and the need to master new materials like copper and silicon germanium. Chipmakers will be under increased pressure to speed designs through the fab and achieve profitable yields in record time to meet an ever-shrinking market window. The target time for bringing a 0.13 µm fab on-line today is half the time it was for a 0.5 µm fab a few years ago, because of the need to get a quick return on investment.

Compounding these pressures is a shift in yield loss mechanisms from contamination-based random effects to design feature-based systematic effects. Yield loss is increasingly driven by incompatibilities between new, ever more complex designs and new manufacturing process technologies.

The IC makers destined to succeed in the coming turnaround will be those capable of effectively integrating design and processes before production starts by analyzing interactions among the traditionally disparate functions of design, process and manufacturing.

Chipmakers that adopt a design-to-silicon-integration approach to proactively deal with product yield and performance issues, and efficiently make the design and process modifications needed to achieve high initial yield at product introduction, will be the winners. They will be the companies to slash the time-to-volume production and reap the rewards of faster time-to-market, lower costs and higher profits.

At SEMICON West 2002, we believe a key trend will be the industry's focus on collaborative efforts between companies. Collaboration is both an economic necessity and requisite to keeping pace with technology roadmaps. The complexity found in tomorrow's integration problems is forcing suppliers, OEMs and chip manufacturers to rethink their business interaction models. How do they protect their portion of the value chain and IP, while at the same time openly share in an effort to increase learning cycles and reduce development costs?

Semiconductor manufacturers are demanding that suppliers and OEMs assume more and more of the development responsibilities for new technologies in an effort to increase fab productivity.

This is a good strategy if the supplier base has the resources to shoulder such responsibilities. However, in the current migrations to 300 mm, copper, low-k and multiple integration schemes, many problems are too complex for suppliers and OEMs to solve.

The industry is disciplined enough to realize that problems are solved when they get defined, and that the better-defined problems are solved sooner with better solutions. What if, in the future, the only way to protect your place in the value chain (and therefore your very existence) is in direct proportion to how collaborative you are?

SEMICON West 2002 will showcase the progress of metrology vendors in addressing the technical challenges identified in the 2001 updated ITRS. Continuous advances in IC technology have propelled semiconductor manufacturing technology to stay on the Moore's Law growth curve. The emphasis now is on shrinking the transistor itself — this requires innovations in gate dielectric films. Metrology for gate dielectric characterization is in the ITRS yellow zone for the 90 nm node, meaning that development is underway. Beyond the 90 nm node, the "research is required" red zone looms. Metrology tools for this node need to be ready for qualification and production use in 2006.

Effective process control for gate dielectric films with the needed precision and repeatability requires the next-generation metrology (now available as stand-alone tools) to be integrated into the process tool. The thicknesses of adsorbed layers of water and organic contaminants are now the same order of magnitude as the process tolerances of advanced gate films. This will be an increasing source of variability, and current strategies to address this problem such as pre-conditioning or isolating the wafer are slow and labor-intensive. Precise metrology can be accomplished within the controlled environment of the process tool and will become an integral part of the process flow. This will require close cooperation between process and metrology tool suppliers (as they become co-owners of integrated metrology) and a high level of metrology tool matching. Cooperative development will provide a turnkey, high-throughput, gate dielectric process control solution to the circuit manufacturer.

Wafer cleaning and surface preparation technology has evolved with the implementation of new materials and processes. The focus continues on maximizing the quality of the gate dielectric, especially as the industry moves toward high-k logic gates, which present new challenges for decontamination of wafer backsides and edge bevels. Smaller chip outlines and higher speeds required from the chip have also led to the introduction of low-k dielectrics and copper conductor schemes, which create additional challenges. Thirdly, increased complexity of next-generation chips is putting enormous emphasis on the requirements for cleaner manufacturing processes to meet performance and productivity needs.

Consequently, a wet wafer market is emerging where multiple technology solutions will be crucial to meet new demands and requirements. Rather than an either/or scenario involving single-wafer wet processing or batch processing, a mix-and-match scenario will be the order of the day at SEMICON West 2002. Single wafer will be the process of choice for critical sub-0.13 µm manufacturing, and batch systems will adequately address non-critical layers for both 200 and 300 mm production.

Chip industry volatility will create a stronger requirement for cost reduction and productivity from equipment solutions so, at the end of the day, the firm with a broad multi-product, multi-application approach will yield the greatest benefit by addressing tougher new customer cost structures and productivity challenges.

Throughout the recent industry slowdown, we saw continued investment in enabling technology for next-generation devices, particularly addressing the adoption of new materials. In the advanced memory market, key equipment selections are being made to support MRAM development. The MEMS market is another segment that continues to invest in new equipment. This is driven by both traditional transducer manufacturing and new optical switching components. In addition, the compound semiconductor industry continues to exhibit signs of resumed growth in acquiring enabling technologies. Indium phosphide is sure to play a big role in the growth of this market moving forward, and this is a challenge for equipment suppliers serving this sector. Adoption of new materials in the wider electronics industry is much more than the buzz over copper damascene and low-k dielectrics. We see an opportunity for companies to extend new materials development as a strategic advantage well into the future. The companies that are able to quickly address and adapt to these new materials and markets are poised to make significant gains as the industry rebounds.

There are two enduring industry trends of particular interest: Moore's Law and the drive toward larger wafer sizes. Looking at these trends, it seems that both could be challenged by economic factors rather than technological limitations. At some point, the benefits of reducing critical dimensions could be totally offset by the increasing cost of the process, defeating the purpose of the continuous drive toward smaller geometries. The cost of process development now requires the formation of alliances to share the burden. Tower, for example, based its 0.18 µm process on Toshiba's technology baseline. Additionally, the move to 300 mm eventually may prove to be counterproductive. In spite of what was "demonstrated" on spreadsheets, it has yet to be shown that the reduction in the cost of a square inch (or centimeter) of silicon is, indeed, materializing in the practical world. It is very possible that there are inefficiency factors of the larger wafer size that were not properly considered. One can ask the question: Are we going to slow down at some point due to economic barriers?

The future is in the "pajama-clad" process engineer. While this may be a slight exaggeration, it's not far from reality. E-diagnostics makes this possible by allowing remote monitoring and troubleshooting of production equipment from virtually anywhere, any time, day or night. Demand for e-diagnostic capability is further driven by lean staffing, the need for improved equipment uptime, and the desire for fabwide manufacturing control.

E-diagnostics doesn't stop at the system level. As fabs and equipment manufacturers continue their quest for total system control and operational feedback, electronic monitoring and control is finding its way all the way down to the component level. Trebor has witnessed firsthand this growing demand in our DI water heating systems and chemical pumps.

To accommodate customers' needs, Trebor's new Quantum DI water heaters, for example, offer Ethernet connectivity to provide fully functional system control and monitoring. This enables a technician or the factory, given the IP address and permissions, to access the system for quick diagnostics in the event troubleshooting is required. In addition, this functionality has allowed customers to evaluate our product performance from remote locations. The use of fiber optics has given Trebor pumps a whole new level of control not previously offered by many chemical pump manufacturers. Using a variety of probes and sensors, depending on the application, we are able to provide customers with a diagnostic interface for cycle counting, remote control and leak detection.

While it may not be practical or cost-effective for all significant system components to have fully embedded e-diagnostic capability, the ability to provide an effective interface and tool-level feedback will be essential to achieve the goal of the fully integrated system. We fully expect e-diagnostics to remain a hot topic at this year's SEMICON West.

A trend that will be evident at SEMICON West entails the ongoing development and implementation of low-k dielectrics. As devices shrink, the capacitive coupling between interconnects becomes a speed-limiting issue. Integration of low dielectric constant (k value) insulators with copper damascene architectures remains one of the few unsolved technical issues for future semiconductor devices. So far, no materials solutions have established themselves, and device makers are presently designing around this issue. However, the requirement for a low-k dielectric for copper still remains, and all the leading CVD equipment and spin-on materials companies continue to develop solutions.

A damascene dielectric structure must satisfy an extremely broad range of sometimes competing process integration requirements. It must plasma etch well, function as a barrier and etch stop, and withstand PR strip and copper CMP.

This is extremely difficult to achieve with a low-k material because the dielectric constant is a function of material density; the lower the density, the lower the k value. This reduction in density compromises the ease of integration of the dielectric material.

As the size and complexity of semiconductor fabs increases, factory automation is becoming increasingly important in driving down overall CoO. ITRS identifies a number of key industry challenges including process control and data communication. Today, fabs have a wide variety of different gas and chemical delivery systems supplied by different vendors, with different local controllers that do not communicate with each other. This makes overall inventory and supply management difficult and time-consuming. The use of industry-standard control platforms that communicate with each other, along with fabwide communication and data acquisition, is essential to meet the identified ITRS challenges of complexity management, factory optimization, extendibility, flexibility and scalability.

Through a standardized approach to control and data communication, the fab operator will have one integrated system to provide real-time process data from gas and chemical delivery equipment, as well as other fabwide systems such as life safety and chemical management. This information will be readily available throughout the fab or remotely through intranet and/or Internet connections, and can be fed directly to overall enterprise management systems. Overall CoO will be minimized through ongoing management of the supply and inventory of process materials and use factors for the delivery equipment for optimal capital deployment. In addition, there will be efficient management of all alarms and remote diagnosis for troubleshooting to ensure that materials are available as required. Control and communications will be designed for rapid addition of new equipment, with automatic configuration for standard items (for example, an additional gas cabinet). Through using industry-standard platforms, there will be extensive support for system upgrades and extensions, and the system design should be modularized to allow local changes without major redesign effort.