Understanding and Reducing Copper Defects

Most high-performance logic manufacturers are by now developing, piloting or producing copper-based circuits. There are a number of companies that introduced copper at the 0.18 µm device node to receive early learning. Such a strategy has helped define and refine process flows and integrated technology while the interconnect features were fairly easy to build (i.e. PVD barrier/seed, electrofill and CMP processes are straightforward to optimize). As feature sizes shrink with 0.13 and 0.10 µm design rules, several changes are required to successfully metalize such structures, which, in turn, can have a negative effect on subsequent processing.

In the copper deposition sequence, there are three main areas where defects can be introduced and have an impact on yield: 1) during barrier/seed deposition (in a PVD tool); 2) during electrofill; and 3) during CMP. Defects introduced in the barrier/seed deposition step are straightforward to identify and address, provided that the appropriate metrology is applied. To this end, close collaboration with the suppliers of metrology equipment has been critical in developing analytical techniques for copper films. Similarly, the ability to analyze and monitor defects on plated films has required optimized metrology methods to lead to consistent results. Measuring copper is difficult, in part, because of its highly reflective surface and large grain size. Early attempts at measuring copper defects consisted of a trade-off between sensitivity and signal-to-noise. To overcome false readings resulting from this high reflectivity, the instrument sensitivity would be reduced, resulting in a very low and inaccurate defect count. Our experience here has led us to primarily use an optical contrast technique as in the KLA-Tencor AIT II system, which is very sensitive, particularly with films thinner than 1 µm. Combined with a defect review capability (optical microscope or SEM), this approach has been very powerful in classifying and addressing defects in a systematic manner.

1. The “swirl” mark is a series of pit defects that follow the arc of rotation of the wafer during plating. It is unique to the electrofill process.

One of the in-film defects unique to the electrofill process is a "swirl" mark (Fig. 1), a series of pit defects that follow the wafer's arc of rotation during plating. Such a defect type is typically associated with incomplete wetting of the copper seed surface during the early stages of plating, resulting in dry spots or bubbles on the surface. As plating proceeds around such a bubble (ranging in size from 0.1 µm to several tens of microns), a circular defect is formed. Factors that contribute to or influence the occurrence of such defects, and that affect the wetting of the surface in the plating solution, include:

• Copper seed age or oxidation state.
• Additives in the chemistry that are strong surfactants.
• Flow dynamics of introducing a (dry) wafer into solution and the onset of plating.

The first factor is not only a function of the time between seed deposition and plating, but also the specific deposition equipment (PVD vacuum quality, cleanliness of the loadlocks, especially during venting, etc.). Some users have resorted to imposing a time window between seed deposition and plating to get consistent results.

The second factor, chemistry, usually cannot be freely modified to address this defect issue — the overriding requirements for chemistry are the fill capability and material properties. However, some additives used for meeting the fill and uniformity requirements tend to act as good surfactants, which help improve wetting and reduce these pit defects.

2. Reduced defect counts were obtained through characterization and modeling, and minor changes in the flow pattern and wetting step.

Although post-plating defects may have a yield impact, this relationship is difficult to establish. Not all wetting-related defects result in line opens or shorts on the interconnect structures, especially if they are situated in the field (non-active) areas of the wafer. Also, damascene trenches and vias act as good capillaries, and can assist the wetting inside features. Post-CMP defects, however, can more easily be correlated to yield loss, as scratches, missing metal and remaining metal can be linked to opens and shorts. Although a number of defect types are attributed primarily to the CMP process (e.g. scratches), there are others that are simply "revealed" or "enhanced" during CMP, while they originated in one of the preceding steps. For example, an incompletely filled structure may not be detecting post-plating if the overburden has completely covered the underlying defect. Such a defect may be more easily observed post-CMP.

3. A “mousebite” defect is where metal is missing, typically on one edge of an interconnect.

4. Post-plating anneal conditions and the choice of a plating chemistry and process can impact the number of post-CMP defects. (Data based on 50% die inspection using KLA 2138 tool.)

Again, this hypothesis has not been proven directly, but there are indirect clues to suggest such a mechanism. For example, the choice of a post-plating anneal condition can have an effect on the incidence of these defects, presumably because it results in grain growth. Also, the choice of a plating chemistry and process (current profile) can impact the number of post-CMP defects. Plating conditions that include reverse currents have been shown to create unfavorable conditions that result in higher post-CMP defects than forward-only (dc) currents. Similarly, chemistries that have certain additives also affect the number of post-CMP defects (Fig. 4).

5. Lower temperatures (<200°C) are required to prevent void formation during annealing.

6. Via pullout voids caused by thermal cycling can result if the damascene features are not sufficiently annealed.