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Consortiums Address Advanced Packaging Requirements

Peter Singer, Editor-in-Chief -- Semiconductor International, 6/1/2002

Two competing consortiums — the Advanced Packaging & Interconnect Alliance (APiA) and Semiconductor Equipment Consortium for Advanced Packaging (SECAP) — are now addressing the requirements of advanced packaging, including flip chip/wafer bumping, chip-scale packaging (CSP), redistribution (RDL) and wafer-level packaging (WLP). APiA was launched in December 2001, and SECAP was announced in July 2000. Both consortiums are largely made up of suppliers that hope to demonstrate that they have developed integrated solutions to today's packaging challenges.

Such consortiums could prove to be a boon to the packaging industry, particularly for contract packaging houses that have limited funding for advanced R&D. Compared with conventional solutions, new packaging techniques such as WLP offer reduced cost, higher-density input/output (I/O), reduced interconnect resistance, better high-frequency impedance, reduced cost over wire bonding, and smaller packages. The challenge is that these new techniques require fine-line lithography, thin-film deposition and metrology tools similar to those used in front-end semiconductor processing.

Wafer bumping used in flip-chip packaging, for example, involves the deposition of under-bump metalization (UBM) by sputtering, which can require three different metals such as aluminum-nickel vanadium-copper (see "Sputtering Faces New Challenges for Vias, UBM"). This is followed by deposition, exposure and development of a relatively thick layer of photoresist, descum, electroplating, resist strip, UBM etch and, finally, reflow. RDL is an additional level of wiring that repositions I/O pads from the perimeter to alternative locations on the chip (Figure ).

Advanced packaging can employ wafer bumping and RDL, which have benefits in terms of higher I/Os, reduced cost and better electrical performance. (Source: August Technology)
Here's a summary of the two consortiums:

APiA

ApiA, the newest consortium, is focused on "accelerating the development and implementation of commercially viable, comprehensive and risk-free packaging solutions that address the escalating manufacturing and performance challenges of leading-edge chipmakers worldwide. As such, the alliance will concentrate on enhancing the productivity of the equipment and process solutions critical for advanced packaging and interconnect processes, as well as developing guidelines and standards to enable easy adoption of these sophisticated solutions."

Founding members are August Technology Corp.; Casio Computer Co. Ltd.; Dainippon Screen Manufacturing Co. Ltd.; EBARA Corp.; Kulicke & Soffa, Flip Chip Division; Ultratech Stepper Inc.; and Unaxis Balzers Ltd.

APiA will concentrate on bump processing and WL-CSP, and plans to establish 300 mm pilot lines in Asia and the United States for use by alliance members and customers. Customers will be able to evaluate a working 300 mm advanced packaging process line, collaborating with each individual supplier to evaluate tools and process technologies. The 300 mm pilot lines will allow member companies to work together in technology development, creating a process for turnkey advanced packaging solutions.

To date, APiA has held seminars at various SEMICON shows (Japan, Taiwan, China), and plans another at SEMICON West on July 18.

SECAP

SECAP's mission is "to support the advanced packaging industry by delivering optimized process equipment for wafer bumping, wafer-level packaging and HDI technology. The membership of SECAP is limited to equipment and material suppliers in order to maintain SECAP as an efficient and trustworthy resource to the advanced packaging industry."

Member companies include SUSS MicroTec; Semitool; Image Technology Inc.; The Fraunhofer Institute for Reliability and Microintegration (IZM); Electroglas Inc.; and Matrix Integrated Systems.

The next seminar SECAP will host, "Peaks in Packaging," is this month in Whitefish, Mont., followed by "Wafer-Level Packaging," to be held July 23 in San Francisco.

For additional information on assembly and packaging, go to www.semiconductor.net/assembly

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