SI CHINA     SI JAPAN
Login  |  Register          Free Newsletter Subscription
Subscribe
Email
Print
Reprint
Learn RSS

In-line Testing Speeds Reliability Evaluations

Laura Peters, Senior Editor -- Semiconductor International, 6/1/2002

The old saying "time is money" applies to many aspects of the semiconductor industry, including reliability testing. While engineers have typically relied on package-level, time-dependent dielectric breakdown (TDDB) testing to qualify gate oxide integrity, the delayed results and high cost make a case for wafer-level testing if the correlation between the two is sufficient. Recently, researchers from Analog Devices (Limerick, Ireland), the Institute of Technology Tralee (Kerry, Ireland) and the National Institute of Standards and Technology (NIST, Gaithersburg, Md.) confirmed a correlation between charge-to-breakdown (QBD) testing at fixed initial current — the conditions most commonly used in production manufacturing — with package-level TDDB reliability results.

They also determined that QBD testing at fixed initial current density, most commonly reported in the literature, also correlates with packaged device results. The research led to control limits that can be readily used in manufacturing to qualify gate oxide reliability and predict product lifetimes. The findings were reported recently at the IEEE International Reliability Physics Symposium in Dallas.

The researchers conducted the ramped QBD tests on 15-nm-thick oxide films of various areas on NMOS and PMOS transistors as well as n-type and p-type capacitors, using 16-unit sample size per test for the structures. Oxide areas, rectangular in shape, spanned seven orders of magnitude, from 4.5 × 10-9 cm2 to 1 × 10-2 cm2. Test conditions were 8 MV/cm at 225°C. The devices were packaged in 18-lead ceramic packages and tested by applying a logarithmic current ramp until the voltage dropped 15%, constituting oxide breakdown. This sample size, generated since the product was released, was deemed sufficient as extensive characterization and monitor data. All tests were performed in accumulation mode. The data indicated gate oxide behavior that is purely intrinsic.

The results demonstrated a distinct area dependency on failure QBD. In subsequent studies on 7 nm devices with the same methodology, the researchers found that the area dependency actually becomes more severe on thinner films, as was expected from previously published studies.

The fixed initial current studies (10 µA ramped to Imax of 100 mA) were conducted at 5.5 V using a 5 sec step duration and 100 msec sample rate. Weibull distributions of the packaged devices showed an area dependence — the smaller the capacitor area, the longer the time to failure. However, probability plots of the wafer-level time to breakdown (TDB) showed an inverse relationship — the smaller capacitor areas failed more quickly. The relationship between reliability data and capacitor area (A) can be described as:

TDDB = 7580A-0.1617

TBD = 1363A0.31

Extrapolation gives the relationship between wafer-level reliability and packaged results as:

TDDB = -15,843ln(TBD) + 105,300

In a similar fashion, the n-type capacitor data gave:

TDDB = 2101A-0.2277

TBD= 2560A0.3822

TDDB =-13,3021ln(TBD) + 76,954

The faster TDDB with larger areas is due to the larger probability of forming a conductive path as the device area is increased. By applying fixed current density to a range of capacitor areas, the researchers expected to see the same relationship with oxide area for QBD as with TDDB.

Next, the group studied reliability behavior with fixed initial current density. When current density was fixed (0.1 A/cm2) and current was ramped to 100 mA, the smaller capacitor area took a longer time to fail on p-type devices.

Control charts were generated based on the Linear E equation, which translates accelerated test conditions to use test conditions for an operating lifetime of >10 years (<0.1% cumulative failures) for any oxide area. The charts can be used to replace TDDB tests with in-line QBD data monitoring.

For additional information on yield management, go to www.semiconductor.net/yield

Email
Print
Reprint
Learn RSS

Talkback

We would love your feedback!

Post a comment

» VIEW ALL TALKBACK THREADS

Related Content

Related Content

 

By This Author

SPONSORED LINKS



 
Advertisement
SPONSORED LINKS

More Content

  • Blogs
  • Podcasts
  • Videos

Blogs

Videos

Advertisements





NEWSLETTERS
Plug in and get the latest SI news, trends and industry updates delivered free, directly to your inbox!

SI NewsBreak and Special Reports (Weekdays)
Wafer Processing Report (Monthly)
Lithography Report (Monthly)
Metrology Report (Monthly)
Clean Processing Report (Monthly)
Packaging Report (Twice Monthly)
©2008 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
Use of this Web site is subject to its Terms of Use | Privacy Policy
Please visit these other Reed Business sites