Integration of CMP with Low-k Materials

The integration of low-k materials is a challenge because of the variety of materials being evaluated and the evolution toward increased porosity. Verifying the compatibility of low-k materials with chemical mechanical planarization (CMP) is essential to confirm the mechanical integrity of a low-k film. This confirmation can be made visually after the CMP polish to determine whether scratching or delamination of the films has occurred.

We studied three types of low-k materials with k~2.0-2.7. Wafers deposited with carbon-doped chemical vapor deposition (CVD) oxides and a variety of inorganic and organic spin-on dielectrics (SODs) were subjected to CMP using different Rodel slurries. The inorganic SODs included Shipley's porous Zirkon low-k and Dow Corning's FOx flowable oxide and porous XLK materials.¹ The organic SODs were Dow Chemical's SiLK and porous SiLK version 7 film.^2,3 In addition, the CVD group at Dow Corning contributed PECVD (plasma-enhanced chemical vapor deposition) SiCOH low-k and amorphous hydrogenated silicon carbide (a-SiC:H) materials based on Z3MS (trimethylsilane).^4-17 The a-SiC:H film was studied to assess how using it as a capping or hard mask layer impacted CMP. Because integration schemes may require CMP to remove or stop on a-SiC:H, it is important to develop chemistries that have both high and low removal rates.

The low-k films were subjected to CMP using both non-selective and selective barrier CMP slurries and a planarizing interlayer dielectric (ILD) polishing slurry. The dielectric constant of each low-k film was compared before and after CMP to observe whether CMP affects the k value. The importance of modulating a-SiC:H removal rates for future technologies integrated with low-k films is addressed here, along with the hardness, modulus and thermal expansion coefficients of the low-k materials. The occurrence of delamination and scratch defects during CMP also is discussed.

Polishing experiments were performed on the Applied Materials MIRRA platform. Low-k CVD and SOD non-patterned blanket 200 mm wafers were polished for 1 min using an IC1010 pad and three Rodel barrier CMP slurries. The pad was conditioned using a Diagrid pad conditioner for 30 min. The polishing conditions for all non-patterned low-k wafers were 3 psi head-down force, 120 rpm platen speed and 114 rpm carrier speed. After barrier CMP, each low-k wafer was buffed on a Rodel film-based poromeric pad for 1 min to remove particle defects on the surface of the wafers. Process conditions for the buff step were 3 psi head-down force, 80 rpm platen speed and 80 rpm carrier speed.

1. Removal rates of non-selective and selective barrier slurries, and a planarizing ILD slurry used to polish 200 mm a-SiC:H. The a-SiC:H thicknesses were ;1000 Å.

Defectivity measurements were first performed on the Applied Materials Orbot WF720 patterned and non-patterned wafer inspection tool to obtain the total defects for each low-k wafer. The wafers were then viewed using the Leica ErgoPlan optical microscope for defect characterization and classification. Defectivity work was performed pre- and post-CMP.

Contact angles were measured on the Kruss K12 tensiometer. One measurement cycle with a 0.2 mm data acquisition step was used. Advancing and receding depths were 5 mm. The measurement speed was 3 mm/min and the surface detection sensitivity was 0.01 g. Only advancing contact angles are reported.

Non-selective barrier, selective barrier and planarizing ILD slurries were used for CMP integration with low-k films. The planarizing ILD slurry is designed for topography correction and planarization of the ILD film after successive stacking of metal layers in dual-damascene integration architectures. The first objective was to better understand how CMP affects the final k value.

Table 1 lists the calculated average k values of five low-k materials and a-SiC:H, before and after CMP. Including standard deviations, the dielectric constants for SiLK, porous SiLK (v7) film, SiCOH and a-SiC:H did not increase after CMP. Results also show that CMP will not increase the k value of a CVD, dense SOD or relatively closed-pore, SOD-type low-k film. In addition, the dielectric constant of a-SiC:H is not affected by CMP for integration architectures that will incorporate a-SiC:H hard mask capping materials over the low-k films.

An increase in k was observed for the mostly open-pore XLK film, which also had the lowest dielectric constant. In theory, k_eff is inversely proportional to the pore volume fraction. An increase in the number of pores, or a transition from a closed- to an open-pore dielectric film, should lower the dielectric constant of the material since the addition of pores incorporate more air (k=1.0) into the film. The difference in pore volume for XLK vs. the other porous films is believed to cause the increase in k for XLK.

The reason behind the increase in the XLK dielectric constant during CMP is not well understood. But it is believed that water from the CMP slurry may be absorbed into the dielectric material during polishing of blanket low-k films, hence increasing the dielectric constant. Chemical components from the slurry such as abrasives or surfactants might also become trapped in the film, further increasing k. This suggests that, as copper/low-k ULSI schemes incorporate low-k materials with k≤~2.0, capping materials will become critical to preclude an increase in k during CMP. However, it is important to note that a post-CMP heat treatment of the low-k film may lead to a partial or full recovery of the k value by removing liquid residues trapped in the pores. This option might be considered to remove trapped liquids either prior to depositing the cap layer, or to recover the k value, averting the need for a cap layer.

There is no consensus on a favored integration scheme with respect to hard mask capping layers for low-k materials. In fact, the multitude of low-k materials probably will require several hard mask integration architectures and, at least initially, might preclude one favored scheme from being chosen. Hard masks will be integrated on top of the low-k dielectric, or the low-k dielectric will be sandwiched between a top and bottom hard mask layer. Hard masks will be used mainly as etch stops and/or as diffusion barriers against copper metal. One main variation in integration schemes will be in the hard mask design; the low-k material can be integrated into either a single- or dual-top hard mask integration architecture. The second will be in the choice of hard mask material. For the single-top hard mask scheme, a-SiC:H, SiO₂ and Si₃N₄ are all possible capping layers. For dual-top, combinations of SiO₂/a-SiC:H, SiO₂/Si₃N₄ and Si₃N₄/SiO₂ are all likely candidates.

The above-mentioned CMP possibilities for low-k integration require consideration of how much to polish or remove a capping material during CMP. Because SiO₂ and Si₃ N₄ polishing is being done, the novel material to be integrated with low-k materials will be a-SiC:H.

A non-selective barrier slurry, a selective barrier slurry and a planarizing ILD slurry were used to polish 200 mm a-SiC:H wafers provided by Dow Corning using a Rodel IC1010 pad. The a-SiC:H thicknesses were about 1000 Å (Fig. 1).

Two significant results were observed in the a-SiC:H polishing test. First, using an IC1010 pad at process conditions of 3 psi × 120 rpm × 114 rpm for a polishing time of 1 min, both the non-selective barrier and planarizing ILD slurries removed most of the a-SiC:H material. The removal rate was ~940 Å/min. This is useful for designers requiring partial or total removal of the a-SiC:H hard mask. Second, the selective barrier slurry removed minimal a-SiC:H material, exhibiting an average removal rate of ~13 Å/min. Therefore, the selective barrier slurry will be advantageous for customers requiring either minimal a-SiC:H removal during CMP, or needing CMP to stop on the a-SiC:H hard mask. Partial removal of the a-SiC:H hard mask can be obtained by tuning the chemical composition of the slurries, thus modulating the a-SiC:H removal rate to meet a specific customer requirement. Consequently, the work has shown that we can completely remove, partially remove or leave intact the a-SiC:H material with either barrier and ILD planarizing slurries, and can therefore tailor slurries to meet future a-SiC:H hard mask integration challenges.

Effective cleaning of low-k materials will be critical to meet future defectivity success criteria. Two potential areas of concern are hydrophobicity and defectivity.

First, as a result of reducing the dielectric constant, many of the low-k materials are hydrophobic when compared with traditional TEOS SiO₂ films. A qualitative assessment of hydrophobicity can be made by visual inspection. When the contact angle is reported as non-zero, a convex bead of water is observed on the surface of the wafer, resulting from the higher surface tension between the low-k film and the water. Conversely, when the contact angle is zero, the water will spread and lay completely flat on the wafer surface. Therefore, the low-k materials are more hydrophobic than the TEOS SiO₂ films, making it critical to understand which chemicals best modify surface hydrophobicity to meet future-generation defectivity success criteria. Table 2 gives the average contact angles of various low-k materials with DI water, measured before and after CMP.

2. Optical microscope images of delamination defects from low-k Type A.

Another concern related to cleaning of low-k materials involves scratching and delamination defects associated with high residual stresses, as well as differences in modulus and thermal expansion coefficient of low-k films and other device materials. The hardness and modulus of low-k materials are lower than the traditional PECVD SiO₂ dielectric. The coefficient of thermal expansion (CTE or α) of the low-k materials also is significantly larger than the CTE for PECVD SiO₂ . The stress of the material is a function of both the modulus of elasticity and the strain, and is given in Equation 1:¹⁸

(1)

For stretching or compressing, stress is defined as force F divided by the area A over which the force is applied. The modulus of elasticity for tensile/compressive stresses is called Young's modulus and is represented by E, and the strain is defined as the fractional change in length of the material, ΔL/L. The equation for stress is further defined in Equation 3 as a function of the CTE, by using the definition of CTE in Equation 2 and substituting for strain in Equation 1.¹⁸

(2)

(3)

Therefore, it is shown in Equations 1 and 3 that stress is a function of both Young's modulus E and the CTE. Accordingly, an increase in either E or CTE will increase the stress in the film. Moreover, a disparity in the CTEs of the low-k materials vs. the under/overlying films can create a tensile stress in the low-k film and may lead to stress corrosion, cracking or delamination.¹⁹ The cohesive strength of the low-k material with either the substrate or underlying film layer must be sufficient to prevent delamination of the low-k film.

3. Average delamination observed after CMP processing on five types of non-patterned CVD, SOD and porous SOD low-k materials. Defectivity of blanket a-SiC:H films is shown as Type B.

4. Optical microscope images of scratch defects from low-k Type D.

In Figures 2 and 4 we include representative and typical optical microscope images of delamination and scratch defects observed on the low-k films post-CMP. Figures 3 and 5 summarize the classified average delamination and scratch defects observed after CMP on five types of non-patterned CVD, SOD and porous SOD low-k materials. The defectivity of blanket a-SiC:H films from Dow Corning ("Type B") also were compared with the low-k films. Note that the average total number of defects observed for each low-k material was in the thousands, whereas the average total number of defects for the a-SiC:H material was about seven. Consequently, to understand the types of defects observed on each low-k material, about 150 of the total defects were classified. In Figures 3 and 5, except for a-SiC:H, the classification of about 150 of the total defects is shown for the low-k materials. The defectivity work showed that each low-k material had a high number of at least one defect type. In the classification, the highest average number of defects observed for any low-k type was as high as 42 counts of film delamination and 150 counts of scratch defects. The a-SiC:H material also had the lowest number of total defects. There were about seven observed occurrences of a-SiC:H delamination and no observed scratch defects. The high defectivity occurrences on each of the low-k films, coupled with the a-SiC:H materials' low defectivity counts, indicate that capping will be necessary and desirable for future technologies to successfully integrate low-k ILD/IMD materials.

5. Average scratch defects observed after CMP processing on five types of non-patterned CVD, SOD and porous SOD low-k materials. Defectivity of blanket a-SiC:H films is shown as Type B.

CMP was integrated with CVD and SOD low-k materials to demonstrate compatibility of low-k films with standard CMP process conditions and consumables. Given the multitude of low-k ILD/IMD materials available in the marketplace — and the variety of integration schemes that are anticipated — it is apparent that a range of CMP consumables will be required to meet the needs of device manufacturers. Rodel has developed several CMP consumables and process solutions designed for successful integration of low-k films into ULSI production.

We concluded that one can modulate and tune slurry chemistries to meet customer-specific non-patterned removal rate or selectivity requirements for a-SiC:H materials. In this work, only the CMP slurry was varied. However, by varying the full consumables set, selectivities and removal rates can be further optimized for specific applications.

In addition, the durability of non-patterned low-k materials during CMP suggests integration challenges for low-k materials that are not capped or protected with a hard mask material. The amount of scratching and delamination was significant on the low-k materials, but minimal on the blanket a-SiC:H films. Furthermore, an increase in the dielectric constant was observed for the open-pore low-k material, which had an initial k of ~2.0. The results strongly indicate that capping materials will be necessary to maintain the original dielectric constant of the low-k film for porous materials with k values <~2.0, and will prevent delamination and scratching during polishing. Rodel will continue to focus on verifying these results using patterned wafers and blanket wafer uniformity data. Future reports will include leakage currents and breakdown field comparisons.