Sputtering Faces New Challenges for Vias, UBM

For depositing metals and some dielectrics, there's simply no better technology than physical vapor deposition (PVD) by magnetron sputtering. The concept is relatively simple and time-tested: A "target" of the material to be deposited is placed on an electrode (the cathode) of a high-voltage power source. The wafer/substrate is placed on a platen near the target, usually beneath it. A plasma, typically of argon, is created at the cathode, confined by permanent magnets or electromagnets. Ions from the plasma strike the target, releasing material through momentum transfer. These sputtered atoms leave the target in all directions, and some of them deposit on the wafer surface (Fig. 1)

Sputtering is used for a wide range of applications. In fact, almost every electronic device has some layer that's been deposited by sputtering.

In advanced microprocessors, sputtering is used to deposit the tantalum and tantalum nitride diffusion barriers, copper seed layers, and the titanium and cobalt used for silicide formation at the source and drain contacts. In memories, it's used to deposit blanket films of aluminum (many DRAM makers have yet to make the transition from aluminum to copper) and some types of high-k dielectrics, such as lead zirconate titanate.

In gallium arsenide devices, there's interest in moving away from metal evaporation systems to sputtering systems for the mostly gold-based interconnects. In hard disk drives and read-write heads, sputtering is used to deposit extremely thin layers of magnetic materials.

Novellus' INOVA xT PVD system delivers copper barrier/seed layers for 100 nm and beyond. (Source: Novellus Systems)

Not surprisingly, these applications are driving new developments in sputtering technology and equipment in different ways. For some applications, such as surface acoustic wave (SAW) or bulk acoustic wave (BAW) devices, the goal is to achieve blanket deposition with extremely good uniformity, very low particle counts, and very low cost.

In other applications, particularly where the material is deposited in high-aspect-ratio vias (i.e. advanced microprocessors), it's crucial to obtain good film step coverage. These divergent requirements have led to the development of PVD tools with radically different designs, ranging from in-line batch tools to single-wafer cluster tools.

"The biggest innovations have been driven by the need for improved step coverage, which has led to collimation and long-throw sputtering techniques and, more recently, to ionized PVD," said Dana Tribula, chief marketing officer for copper, PVD and integrated systems at Applied Materials (Santa Clara, Calif.). These are all designed to give added directionality to the sputtered material to help ensure that it reaches the bottom of a feature (i.e. a deep via hole).

1. In magnetron sputtering, material erodes from a target and lands on the wafer. Shown is Trikon’s AHF system, which combines high electric and magnetic fields to generate ionization. With the coils off, it becomes an LTS module; with coils on it’s I-PVD. (Source: Trikon Technologies)

Despite the relative simplicity of sputtering theory, modern sputtering systems are actually quite complicated. Beyond such obvious differences as cluster tool vs. batch, you'll find major differences in the configuration (sputter-up, sputter-down, sputter-sideways); type of power supply (dc vs. rf vs. pulsed pulsed); cathode design (dual, flat or hollow); magnets (permanent vs. electro, fixed vs. rotating); shielding around the plasma; type of bias on the wafer; type of cooling used; and amount of automation. The way in which the source, or target, is designed and fabricated also will have a significant impact on sputtering results.

That's what really counts, of course — the results. In addition to general concerns such as throughput, deposition rate and cost of consumables, the quality of the deposited film properties must be measured in terms of film composition, stoichiometry, step coverage, uniformity, stress, density and number of defects (as well as other electrical and mechanical properties, like conductance and temperature coefficient of expansion).

One important thing to note here is that there are several different ways of achieving various film compositions, such as metal alloys. One way is to deposit from more than one target simultaneously, which is called co-sputtering. Another is to use a target that is itself an alloy, but beware — the composition of the deposited material will rarely be exactly the same as that of the target.

2. In case there is any question about the future of PVD, note this CVD-like step coverage achieved by PVD chamber using the Novellus HCM. (Source: AMD)

Many of the new developments in sputtering over the past few years have been aimed at solving problems associated with getting diffusion barrier and copper seed layers into the high-aspect-ratio vias found in leading-edge chips.

The challenge is to get enough material down at the very bottom of the via, and on the sidewalls, without getting too much overhang at the top of the via. That involves two components: 1) giving the metal flux from the target as much directionality as possible so the metal atoms are striking the wafer at a 90° angle, increasing the odds they will make it all the way to the bottom of the via; and 2) resputtering the material once it does reach the bottom of the via, to increase the coverage of the sidewall and in the corners of the via. In some cases, particularly with barrier films, it's desirable to keep the layer at the bottom thin to minimize via resistance.

3. The trick in sputtering is to add some directionality to the sputtered material to increase coverage in deep features. LTS uses basic geometry, while new SIS ionizes the metal atoms and accelerates them at the wafer. (Source: Ulvac Technologies)

4. The Novellus HCM source achieves ionization through magnetic confinement of electrons within a 3-D target. In contrast, ionization within the rf-enhanced planar magnetron source is a function of the rf power and chamber pressure. (Source: Novellus Systems)

Although collimation and LTS are still widely used for many applications, ionized PVD has emerged as the industry's savior (Fig. 2). With the latest technology, IC manufacturers will be able to continue using PVD for several more device generations, down to 60 nm or below for barrier and seed (see Semiconductor International , May 2002).

"All of the developments around ionized PVD technology are aimed at getting the barrier and seed into higher and higher-aspect-ratio features," noted Wilbert G.M. van den Hoek, CTO and executive vice president of integration and advanced development at Novellus Systems (San Jose). "There is a tremendous desire in the industry to stay with PVD and not go to CVD for those applications." Fortunately, even for demanding applications, PVD can deliver results comparable to CVD (Fig. 3).

I-PVD (Fig. 4) relies on entirely different source technologies to create a much higher-density plasma, ranging from dc-powered hollow cathode magnetron (HCM) to rf-enhanced planar magnetron sources. "One of the key areas in source technology evolution is trying to get the ionization to be as high as possible, and then to be able to control that ion flux," said Julian Hsieh, vice president and general manager of Novellus' integrated metals product business.

The ionization rate of sputtered atoms is a function of the plasma energy and the chamber pressure. At low pressures, the sputtered atoms pass through the plasma region rapidly, and the ionization level is low. As the pressure is increased to several tens of mTorr, the sputtered atoms can be slowed by gas collisions.

As a result, they spend more time in the discharge and are more likely to be ionized.¹ If the percentage of the metal flux that is ionized is made high, the deposition will be primarily directional, and the utilization of the sputtered atoms from the cathode will be high.

"Higher ionization, in general, lets you get more material into smaller features, but the key challenge then is to shape that material into the right step coverage required for the application," said Nirmalya Maity, product manager for Applied's Cu Barrier/Seed Division. Once ionized, of course, ions can be accelerated to the wafer surface by applying a bias to the wafer, where they arrive at almost exactly 90° and with a controllable energy.

A number of companies introduced I-PVD tools several years ago, and have already moved on to second- and third-generation tools. Bias sputtering (BS) is now offered by Anelva, self-ionized plasma (SIP) by Applied Materials, HCM by Novellus, Advanced Hi-Fill (AHF) by Trikon Technologies, and self-ionized sputter (SIS) by Ulvac Technologies.

The second aspect of getting good step coverage is the ability to deposit atoms to resputter the already-deposited film. If the sample potential is made sufficiently negative (i.e. the bias on the wafer is increased), the kinetic energy of the depositing ions will be sufficient to sputter the film and redistribute it within the features. This leads to a thickening of the film in the bottom corners of vias, which is desirable because that location is the most prone to diffusion barrier failure.¹ Argon ions that reach the wafer are also directional and can result in resputtering of material from the top and bottom of the feature.² The limitation of resputtering is that, while it improves step coverage at the bottom of the via, it can increase the amount of overhang at the top of the via (the neutral metal atoms are nondirectional and can cause overhang, since their deposition profile is determined by line-of-sight deposition).

"The resputtering process requires a careful optimization of the metal and argon ion fluxes, so as to maximize sidewall coverage in the via, while maintaining adequate top corner coverage, especially for dual-damascene structures," Maity explained.

However, suppliers are already working to address that as well by optimizing the wafer bias, pressure and power to best control the flux of neutral and argon ions. For example, Mak Tamura, corporate director of semiconductor product marketing at Ulvac Technologies (Methuen, Mass.), stated that the company's soon-to-be-released SIS has good sidewall coverage with much less overhang, while still maintaining high coverage in the bottom. "We are confident that with this new SIS, we can extend the PVD technology to the 70 nm-generation copper."

As previously mentioned, sputtering has applications in almost every electronic device, and it is impractical to go into detail on what are often unique requirements of each film here. However, a few applications are worth noting.

First, although electroplated copper is expected to replace PVD aluminum for many on-chip interconnect applications, there's still plenty of aluminum being sputter-deposited. As a result, there is much activity in trying to improve throughput and cost of ownership, and to reduce defects. There is also still interest in aluminum via-fill processes (a lower-cost alternative to tungsten plugs). "In the memory area, some of the upper levels of interconnects require aluminum fill. We are being continuously challenged by memory makers to improve our aluminum fill processes," Applied's Maity said.

For those in the high-growth area of power semiconductors, there is little alternative to aluminum. Traditionally users of older equipment, new requirements are pushing power manufacturers to materials such as TiN barriers plus bulk aluminum fill into novel designs.

"They need seamless Al layers up to 8 µm thick with near-planar surfaces over shrinking structures. For the PVD supplier, this means designing flow processes while still meeting the aggressive throughput and uptime demands of the cost-sensitive power manufacturer," said David Butler, PVD product marketing manager for Trikon Technologies (Newport, UK).

In the III-Vs area, a push is underway to move from evaporation to sputtering for the gold-based interconnects. "We're suddenly seeing a lot of III-V people looking at the silicon guys, saying, 'I'd like to run like that and get their economies of scale and their cost base,'" Butler explained. "We've been successful in bringing sputter tools to this new breed of III-V people. The directional modules we developed for silicon have two main applications in III-V — seed layer desposition into high-aspect-ratio backside vias, and for lift-off processing. In addition, they like the low defect count and high film density of sputtered layers."

Another exciting application for PVD is the UBM stack used as the foundation for the solder balls (or copper balls) in flip-chip, wafer-level packaging. UBM consists of several different layers of metal, all deposited by PVD. A titanium, chromium or aluminum film is first deposited to achieve good adhesion to the chip surface and a low contact resistance to the metal pads of the die, according to Hans Auer, general manager of advanced packaging at Unaxis Semiconductors (Balzers, Liechtenstein). Next, a barrier metal film such as nickel vanadium or titanium tungsten is deposited, preventing diffusion of the bump metals to the die metals.

Further metals of the sputtered UBM stack are used as seed layers for subsequent plating (copper, NiV or gold), or as wettable material for the solder of printed bumps. Plating bases typically consist of two metals (e.g. Ti-Cu, Cr-Cu, Ti-NiV, TiW-Au), and sputtered full metal stacks for bump deposition by printing consist of three metals (e.g. Al-NiV-Cu).

In backside metalization and UBM, stress control is especially critical to reliable die attachment. Typical sputtered UBM barrier films such as TiW and NiV that are 200-400 nm thick demonstrate extremely high tensile stress of ~1-2 GPa (1-2E10 dynes/cm²). Stress decreases UBM stack adhesion or can even cause delaminating.

Several companies are actively addressing this market with existing equipment — Applied Materials, for example, reports the sale of its Enduras for UBM applications — or with new designs.

The market is still evolving: Companies such as Intel are doing wafer bumping basically as an extension of the front end, while packaging companies and foundries like Chipbond and Amkor are treating it as part of the packaging process. Packaging processes are notoriously cost-sensitive, yet UBM is a challenging application — will batch tools suffice, or is it necessary to go to more expensive cluster tools? Maybe a stripped-down cluster tool is the best solution? Only time will tell.

Here are a few examples of companies addressing the UBM market:

• A new company called Nexx Systems (Wilmington, Mass.), a spin-off of ASTeX, is offering a batch tool called the Nimbus, designed specifically for UBM and capable of handling 100-300 mm wafers with the same platform. Up to five magnetrons are mounted on a pentagon-shaped drum capable of rotating into each of the five positions. Three progressive vacuum stages isolate the process chamber, allowing three batches of wafers to be in the system at any given time.

• Sputtered Films (Santa Barbara, Calif.) offers the Endeavor HT, optimized to meet the demands of the competitive UBM market. Stress control methods developed with the company's S-Gun allow the deposition of high-adhesion NiV films, for instance, with residual stress <170 MPa (1.7E9 dynes/cm²). The Endeavor system has true 5% 3s thickness uniformity on substrates up to 200 mm, and wafer-to-wafer repeatability >1%. It’s similar to the front-end-oriented Endeavor AT but, recognizing the cost-sensitive nature of packaging, does not have many of the gauges found in the AT, and it can’t be used for reactive sputtering.

• Tokyo Electron Ltd.’s (Tokyo) Eclipse Mark IV Lite also is tailored to the unique requirements and operational flexibility requirements of the packaging industry, specifically UBM applications.

• Ulvac has a system called SRH-820 for UBM application. It is a rotational turret system with a seven-process chamber, enabling throughput of >100 wph.

• Unaxis says its Clusterline 300 is designed for "highly sophisticated UBM process applications." It is a cluster tool that can be fitted with up to six modules capable of handling 300 mm wafers. Unaxis also manufactures a 200 mm cluster tool and a batch tool, the LLS EVO, which can be used for UBM applications.

• Veeco Instruments’ (Woodbury, N.Y.) NEXUS system is also capable of UBM, as well as other specialty semiconductor and compound III-V applications, including RFIC gate stack, ohmic contact, thin-film resistors, dielectrics and adhesion/seed layers. It achieves a thickness uniformity of <1% within wafer, wafer to wafer, and run to run.

For more information, check out the Web sites of the suppliers listed below. Furthermore, Reference 1 is a good tutorial on sputtering, and it can be found on the Web at www.research.ibm.com/journal/rd/431/rossnagel.html.