All Dressed Up and Nowhere to Go

Wafer-level packaging (WLP) is one of the revolutionary new packaging implementations of chip-scale packages (CSPs), which have the potential of keeping the package size no larger than the die. Of the more than 20 different WLP approaches, the common theme is that most of the fabrication processes happen at the wafer level, so the manufacturing costs are per wafer rather than per I/O.

One approach, film redistribution and bumping, is a scaled-up version of flip-chip bumping. The final package is a bare die, with a coating of Cyclotene polymer acting as a passivation layer and ionics barrier with 10-60 eutectic solder balls, typically 300-500 µm in diameter. The common ball pitches, based on JEDEC standards, are 0.5-1 mm.

This CSP is designed for direct chip attach to a circuit board substrate with no underfill. Without any special features for taking up the TCE mismatch between the silicon die and the PCB substrate, the large diameter of the solder ball is supposed to provide the compliance. This form of WLP has been in high-volume manufacture for more than five years. According to reports from Kulicke & Soffa (K&S, Willow Grove, Pa.), its Flip Chip Division alone has shipped more than 100 million die fabricated with its Ultra CSP technology, mostly as analog chips and integrated passive devices.

These images show the conventional Ultra CSP (left) and new Polymer Collar WLP (right). (Source: Kulicke & Soffa)

"The failure mechanism has been well known and predictable," said Scott Barrett, director of wafer-level products for K&S's Flip Chip Division. From numerous thermal cycling studies, he and his team have found that the failure mode is cracks on the die side of the solder ball, typically 10-20 µm from the under bump metalization (UBM). By cross sectioning samples every 100 cycles, they have found that two cracks grow from opposite sides of the solder ball: the side farthest from and closest to the die center.

Their clever fix to the problem is to add a turtleneck sweater collar to the base of the solder ball to restrict the creep flow of the solder, where cracks typically form. This support increases the fatigue lifetime by more than 50%. The longer the DNP, the larger the improvement. "Without the polymer collar, the Weibel lifetime limits the pin count to about 8 × 8 solder balls, and this is with a restricted temperature range of 0-100°C," Barrett said. "With the polymer collar, we have parts with 9 × 9 solder balls in production now and expect to be able qualify up to 12 × 12."

An attractive feature of the Polymer Collar WLP is that it does not add any steps to the current Ultra CSP manufacturing process. In the old process flow, after the UBM is applied, a solder flux is screened on the wafer and solder balls are placed on the pads and reflowed in place. In the new process flow, instead of a solder flux screened on the wafer, a special "flux-impregnated epoxy" is screened on the wafer, with openings for the pads. The solder balls are placed on the pads and, during the reflow process, the epoxy softens and forms a fillet at the base of the solder ball.

The epoxy collar extends about 50-100 µm up the side of the solder ball from the die surface. This is the critical region where the cracks form. By taking cross sections throughout the thermal cycling process, Barrett's team was able to determine that the collar completely eliminated the crack formation originating from the inside edge and greatly restricted the crack formation from the outside edge.

For its innovative implementation of increasing the reliability of CSPs, K&S was awarded the 2002 Excellence in Electronic Packaging and Production Grand Award, given by EP&P, a sister publication to Semiconductor International.

For additional information on assembly and packaging, go to www.semiconductor.net/assembly