New Annealing Process Will Speed Chip Production
Brian Dance, Contributing Editor -- Semiconductor International, 5/1/2002
As semiconductor technologies advance, the traditional methods of wafer annealing are rapidly approaching their technological limits. A pan-European collaboration is developing a prototype annealing tool that will be a major advance on existing methods. It will offer faster rise and fall of wafer temperature, simplicity of operation, high wafer throughput, excellent temperature uniformity and low power consumption. It is being targeted at three types of processes: annealing shallow ion implants (spike annealing), annealing silicides, and rapid thermal oxidation.
This work is being carried out under the MEDEA+ contactless anneal and silicides system (CLASS) program (T303). The project leader is ASM International (Bilthoven, Netherlands), and other partners are ASM Belgium (Leuven, Belgium), LETI (Grenoble, France), IMEC (Leuven, Belgium), Schunk Kohlenstofftechnik (Heuchelehelm, Germany), STMicroelectronics (Geneva, France) and Xycarb (Helmond, Netherlands). The system is able to handle 200 mm wafers, and work is underway to develop a system capable of processing 300 mm substrates.
The main methods for conventional annealing all have disadvantages. Conventional furnaces require process durations of 1-2 hr, while temperature control is difficult in high-intensity lamp-heated systems. Faster cooling rates are required, especially for spike annealing. The new approach used by MEDEA+ is to float wafers between — and in very close proximity to — two hot massive blocks that are kept at the process temperature. These blocks are perforated with many narrow channels through which gas flows so that the wafer floats stably without touching the blocks. This achieves extremely efficient heat transfer.
The wafer temperature can rise at the very high rate of >300 and 900°C/sec when floating in nitrogen and helium. If the blocks are of adequate thickness, the temperature across the wafer will be very uniform. The heating of a single wafer has a minimal effect on the temperature of the blocks, so simple temperature control techniques can be used. After being annealed, the wafer moves between two water-cooled blocks, still floating on a nitrogen or helium gas cushion to keep its distance from the blocks. Cooling rates of 200 and 600°C/sec have been achieved in nitrogen and helium, respectively. The heating and cooling of the wafer by conduction, rather than by the traditional radiation, makes the precise control of the heat transfer far easier.
The overall heating efficiency of the conduction system is far better than that of traditional systems, as up to 65% of the heating power fed to the blocks can be used to heat the wafer. In lamp-heated systems, the efficiency is only ~5-10%. The risk of temperature overshoot is also greatly reduced by conduction heating so that only a simple temperature control system is required.
Specific targets for the new technique include:
- Processing single wafers with a throughput of >160 wph in a two-module system, this being significantly faster than that of other systems.
- Attaining uniformity levels of 0.5% in oxidation and 1% in implant annealing applications. This is regarded as essential for future technology nodes.
- Substantially reducing operating costs through the use of simplified heating systems, simpler temperature controls and reduced energy consumption. The target energy consumption is 6-20 kW for a 300 mm wafer system, compared with 250-350 kW for a comparable lamp heater.
- Reliable spike annealing for the formation of ultra-shallow junctions, which is made possible by the very high heating and cooling rates. The researchers say this enables the characteristics of ultra-shallow junctions to reach the known theoretical limits of the annealing process.
ASM has developed and refined the prototype system, and has supplied an additional two prototype systems to LETI and IMEC. The system is already able to satisfy the requirements of a 130 nm CMOS process, and further development is in progress for the production of 100 nm devices by technology that is expected to become standard soon.
For additional information on materials science, go to www.semiconductor.net/materials