Removing Barriers to Low-k Dielectric Adoption

At first, it was the multitude of candidates, none of them ideal, that slowed low-k dielectric progress. Then it was the shifted focus from low-k to implementing copper first in manufacturing. Next, companies tackled the extensive integration issues for low-k dielectrics, including the development of cleaning, CMP, stripping and packaging processes to be compatible with low-k materials. During the past year, the industry became torn between two very different materials: an organic spin-on dielectric and CVD silicon oxycarbide (SiOC:H), also called carbon-doped oxides (CDOs), with manufacturability and extendibility to lower k values being of paramount concern. Finally, a combination of the industry downturn and moves to copper and 300 mm led to a conservative approach to low-k material changes, resulting in almost exclusive use of FSG (fluorinated silicate glass) at the 130 nm device node.

After a delay of two device generations, reflected in unprecedented changes to the ITRS , low-k dielectrics are finally entering production. The bulk of low-k implementation will occur at 90 nm, where CDOs (also called organosilicate glasses, OSGs) and spin-on polymers will dominate at k=2.7.

In bringing low-k films to production-worthy status, engineers have solved a multitude of problems, including integration, yield and reliability issues brought about by the fundamental change to a softer, much more delicate dielectric material than SiO₂. In particular, packaging has been an issue with low-k because much of the early development was exclusively conducted at the wafer level. "There's now a clearer understanding of the threshold of material specifications needed for the device to endure different types of bonding and packaging," said Farhad Moghadam, vice president and general manager of the Dielectric Systems and Modules product group at Applied Materials (Santa Clara, Calif.).

1. AMD’s 130 nm process uses nine levels of metal, Black Diamond low-k dielectric and BLOk dielectric barrier films. (Source: AMD)

"The biggest accomplishment in the last year is that several logic companies have decided to use 2.7 CVD films for their 100 nm processes," said Tominori Yoshida, US Eagle product manager at ASM International (Phoenix). Suppliers have developed ways to improve the film strength (hardness and toughness), which is especially important to integration capability (Fig. 2), Yoshida added.

Another important recent change in CVD OSGs has been the demonstration of films with k<2.5, extendibility that was not previously thought possible. One example is a k=2.2 Orion film from Trikon Technologies (Newport, UK). Most CVD suppliers are offering 2.7 and 2.4 films, and some have demonstrated k~2.0. However, it has taken several years for CVD films to catch up with spin-on materials. "With spin-on, there's a degree of molecular control you can exercise that you don't have with CVD," said Mike Thomas, CTO of Honeywell Electronic Materials (Sunnyvale, Calif.). Spin-on products, with the notable exception of SiLK from Dow Chemical (Midland, Mich.) and GX-3 from Honeywell, include silicon-based systems with carbon (or methyl) groups and/or hydrogen attached. These include XLK from Dow Corning (Midland, Mich.), 2.2 films from JSR (Tokyo), and Nanoglass E from Honeywell Electronic Materials, with tunable k to as low as 1.8. About a year ago, Shipley Co. (Marlborough, Mass.) also entered the spin-on low-k arena. Despite many offerings and the general belief that spin-on materials eventually will be required for ultralow-k (k_eff<2.4), CVD is gaining popularity, largely due to the reuse of toolsets.

2. A 2.7 low-k film integrated in a dual-damascene structure. (Source: ASMI)

Another issue that has slowed low-k adoption is the production demand to not switch multiple times between spin-on tracks (see "Tailoring Tracks for Spin-on Dielectrics," Semiconductor International, April 2002) and CVD chambers. Though the copper barrier cap remains CVD, materials suppliers have devised spin-on stacks that do not compromise k_eff. For instance, Honeywell Electronic Materials employs its various low-k materials (k~2.6-1.8), taking advantage of the selectivity between inorganic (Nanoglass E) and organic (GX-3) films to provide controlled stack manufacturability. Dow Chemical recently introduced spin-on CMP stop (k=2.9), etch stop (k=2.9) and hard mask layers to allow a spin-on stack, which is cured in one furnace step (Fig. 3). "The stack is balancing the competing requirements of etch selectivity, adhesion and CMP removal rates, while delivering k_eff of <2.4," said Mark McClear, Dow Chemical's general manager of semiconductor fab materials.

3. A stack of SiLK (left) and porous SiLK (k=1.9), integrated with Ensemble etch stop (ES), CMP-cap (CS) and hard mask (HM) films, are expected to enable keff~2.4. These processes are in development. (Source: Dow Chemical)

Low-k films must withstand the mechanical and thermal stresses of processing and the electrical stresses of normal device operation. For most low-k dielectrics, the issue is not of creating a low-k film but of maintaining k. After all the integration steps with various etch stop layers, barrier caps on copper, CMP stop layers, etc., only the effective dielectric constant (k_eff) matters. Perhaps this dynamic is as indicative of the reason for stalling low-k implementation, when the final k_eff must offer considerable performance increase (lower RC delay and reduced cross-talk) relative to FSG (k_nominal=3.7, k_eff~4.0) dielectric stacks.

CVD OSG films are available from ASM International, Applied Materials, Novellus Systems (San Jose) and Trikon Technologies. CVD suppliers and customers continue to explore alternative precursors for SiOC films. The first precursors being used in production are Dow Corning's Z3MS (trimethylsilane), tetramethylsilane (4MS) from the Schumacher division of Air Products and Chemicals (Carlsbad, Calif.) and tetramethylcyclotetrasiloxane, marketed by Arch Chemicals (N. Kingston, R.I.) as TMCTS and by Schumacher as TOMCATS. "There will be a lot of learning required to help define what the real needs of the next precursor will be, because they go well beyond reducing k," said Mark Loboda, Thin Film Technology Platform leader of Dow Corning.

Arch Chemicals' Thin Film Systems group is working closely with CVD OEMs to develop new precursor solutions that often involve co-reactants or additive technology, supplementing Arch's supply of high-purity OSG precursors such as DMDMOS (dimethyldimethoxysilane), TMCTS and OMCTS (octamethylcyclotetrasiloxane). These approaches are aimed at improving the quality of the film, or stability of the chemistry, thereby enhancing manufacturability and easing integration.

Wilbert van den Hoek, CTO and executive vice president of integration and advanced development at Novellus, explained, "We've developed a solid understanding of the dynamic between carbon content, precursor type and film qualities. We've learned how to manage the implementation of carbon in the film that enables us to make a lower-k film but with better hardness." The company's first-generation Coral film has a k=2.8 and hardness of 1.5 GPa, but second-generation developments led to even better hardness. "We're going to use that understanding to drive to k=2.4 with a hardness above 1 GPa," he said, emphasizing that such development will offer a substantial improvement over current PECVD films of k=2.5 that have film hardness in the 0.5 GPa range.

Companies are looking closely at the thermal budget of back-end processes. "Your via-1 dielectric will face eight or more thermal cycles, which is likely to affect via resistance, so we are trying to reduce the temperature of nitride barrier and low-k deposition processes below 400°C to reduce stress migration and other effects of thermal cycling," Moghadam said.

Although the low-k films tend to garner all the attention in the low-k marketplace, it is the etch stop, barrier and CMP stop films that allow successful dual-damascene integration. The development of amorphous hydrogenated SiC films (a-SiC:H) with a k=4-6 (depending on deposition parameters) offers the combination of good adhesion to copper, chemical and moisture resistance, mechanical strength and better reliability needed to replace higher-k (7-9) SiN-based barriers.

With SiC-based films, companies tend to add small quantities of nitrogen or oxygen to reduce leakage in the film. "If you add oxygen, it's more challenging to get good selectivity between the low-k and barrier films. And if you add nitrogen, you have a potential risk of photoresist poisoning," said Steve Lassig, senior manager of process integration at Lam Research Corp. (Fremont, Calif). Resist poisoning has turned out to be a bigger problem than originally expected. It occurs when an amine molecule, such as activated nitrogen in plasma chambers, interacts with acidic components in chemically amplified resist to neutralize and prevent its dissolution in developer. Poisoning is addressed through a combination of hard masks and specific integration scheme. But Moghadam notes that, even in cases where resist poisoning is under control, hard masks may be required simply because the resists have gotten so much thinner.

"One of the key challenges with silicon carbide films is that they allow gases and moisture to diffuse through, although they are not porous in the classic sense of having holes in the film," van den Hoek explained. "Though the moisture doesn't absorb in the film because the film is hydrophobic, we still had to develop a silicon carbide film that was impervious to moisture and oxygen diffusion."

Among the ancillary dielectric films, one of the most important is the capping film over the copper line. "We need to perform CuO removal, and how you perform this pretreatment has a profound effect on device reliability and electromigration because it dictates the cohesive forces between the materials," Moghadam said. Other than nitride and carbide films, another alternative, deposited by trimethoxysilane and N₂O, provides a low-leakage film with k~3.9. Researchers from Hitachi Ltd. (Tokyo) found that the film exhibited lower line-to-line leakage current of <10 pA/cm² (at 1 MV/cm, 140°C) and higher breakdown field (>10 MV/cm) than plasma TEOS films.¹

Driving down k_eff

Some IC manufacturers are eliminating the intermediate etch stop layer between the trench and via in common via-first dual-damascene approaches. Lassig explained that this can lead to facet formation that occurs because low-k films have about half the density of FSG or oxide (Fig. 4). During trench etch, faceting refers to etching of the edge of the via opening. Another potential complication during trench etch creates a fence-like residue, where BARC fills the bottom of the via and sidewall polymer residues act as a micomask, causing incomplete etch. A combination of fences and facets results from vias with varying size across the wafer.

4. Elimination of the trench stop requires strategies to manage facet (top left) and fence (top right) formation. One approach involves filling the vias with organic film, etching back to form nearly full plugs and then trench lithography. The lower left SEM shows an SiOC low-k stack with trench lithography over a via, and the center SEM is the same location following etch, in situ strip and in situ barrier open. A FIB cross section (right) through the finished dual-damascene structure shows the via connecting two copper levels. (Source: Lam Research Corp.)

The barrier open process is particularly important. "If you allow any re-entrant angles or undercut, it can result in microvoid formation during thermal cycling, which can grow and lead to reliability problems," Lassig said. Undercut of a feature typically prevents uniform deposition of the Ta/TaN barrier.

Voids in vias are one of the most common long-term reliability problems in copper/low-k processes, according to Nunan. "Companies like to advertise void-free filling processes, but even when there are no voids at time zero, there's always microvoids in the film that have a tendency to coalesce through various thermal and mechanical stresses, which can migrate and open up a via," he said. Claims of void-free vias can only be made after testing several million via chains and tracing each defect to its source, he added.

Many low-k yield problems are tied to copper CMP, Nunan said. "The CDOs are softer films, so obviously they are more susceptible to CMP damage, dishing and erosion. But they're also susceptible to random damage, which can cause topography differences that influence your copper fill and overall, after CMP, shorten your features." None of the low-k films handle sheer stress as well as undoped oxides, he added, and post-CMP cleaning has to be done in a way that doesn't create an opportunity for photoresist poisoning. "With copper and low-k, we find that customers have changed their inspection routines and are using voltage contrast much more often to look at electrical defect signatures."

Lam's Simon McClatchie, senior integration manager, said, "People have been focusing on the robustness of the materials, but integration issues that cause, for instance, adhesion failures depend on stack strategy and material choice." Most low-k films are susceptible to wafer-edge peeling or delamination, a problem that is even more challenging on 300 mm wafers, he said. McClatchie explained that a number of strategies address this concern — including design, adhesion-promoting treatments and improved CMP downforce control.

Post-CMP cleaning is more difficult because the low-k films are typically hydrophobic. Several materials suppliers, including Arch Chemicals (Norwalk, Conn.), Ashland Specialty Chemical (Dublin, Ohio) and EKC (Hayward, Calif.), have developed specific solutions for copper and low-k residue removal.

With the maturing of low-k, companies are getting more involved in the integrated device aspects of performance. "We are shifting a lot of our attention to reliability — understanding what the data means so that we can guarantee that the electrical stability of our material is on par with that of SiO₂," said Dow Corning's Loboda. The same delay to next-generation materials that occurred with FSG might apply to porous low-k films. "Now that FSG is holding onto life, maybe you will find that some of these 2.7 materials are going to be around a lot longer than the R&D groups might want to admit."

Industry learning over the last several years has led to a better understanding of porous materials. While low-k CVD films were once referred to as "low-density," many companies now call these films porous because the space behaves much like pores in spin-on materials at the sub-100 nm scale. Pores in spin-on materials can be formed using a variety of techniques, then delivered to the wafer, whereas the techniques in CVD are tied to the on-wafer process.²

5. Dual-damascene integration of porous SiLK (k=1.9) required no change in cleaning chemistries and allowed 6 psi down-force CMP. (Source: IMEC)

But others, such as Honeywell's Thomas, refute the idea of a significant difference between open and closed pores. "Our studies indicate that transport phenomena in dielectrics is much more a function of diffusion and solubility of the material rather than whether the pores are open or closed," he said. "Small molecules, such as hydrogen, water, carbon dioxide and fluorine, can be freely transported in and out of the material."

There is also industry debate over necessary pore sizes, which range between 5 Å (for ASMI's Aurora 2.4 film) and 100 Å (for porous SiLK). Whereas 10% of the device feature size was used as an early rule of thumb, much yield and reliability data is needed before a necessary pore size and pore volume (percentage of pores in the film) can be absolutely determined. These issues and countless others, will be resolved long before porous low-k dielectrics will be brought into manufacturing.