MEDEA+ Project: ALD for Deep-Submicron Devices

A European consortium is developing an atomic layer deposition (ALD) process that will allow the controlled deposition of atomic-scale multilayers, including those required for the dielectric materials of CMOS devices with gate lengths of 100 nm or less. This atomic layer chemical vapor deposition (ALCVD) technique, known as ALAD1N+, is a continuation of work that started under MEDEA and is currently referred to as MEDEA+ project T302. It extends earlier exploration of a promising process for the fabrication of atomic-scale multilayers. Unlike conventional CVD, ALCVD allows successive monolayers to be added with precise control of thickness and composition of each layer, even if the underlying topography is irregular.

ASM International (Bilthoven, Netherlands), holder of the patents, is coordinating the project. The consortium partners are IMEC (Leuven, Belgium), ASM Belgium (Leuven), ASM Microchemistry (Espoo, Finland), LETI (Grenoble, France), Philips Semiconductors (Eindhoven, Netherlands) and STMicroelectronics (Geneva). The companies believe this project will pave the way for production-ready tools and give Europe a valuable lead in the fabrication of future generations of chips. The project began in January 2001 and continues until June.

The scope of the work has been widened under MEDEA+ to include three applications. Processes and equipment are being developed for gate dielectrics and gate electrodes, as well as for the barrier and seed layer deposition of dual-damascene structures of inlaid metal interconnects. An initial investigation into ALD for inter-poly dielectrics also is planned.

It originally had been assumed that ALCVD would be essential for the production of 100 nm devices. However, it probably will not be used until the 70 nm node, anticipated for 2005, because of recent progress in conventional techniques. In ALCVD, the substrate is exposed alternately to the separate gas phase precursors. Each of these covers the substrate with less than a single atomic monolayer. The deposition conditions can be optimized for each separate precursor, and gas flow maintained for the time required to ensure that a uniform chemisorbed layer covers the whole surface, including even the bottoms of deep trenches. This contrasts with conventional CVD, in which two gas compounds are present in the reactor at the same time, thus making accurate control far more difficult.

Early results from ALCVD stand-alone equipment showed it has the ability to form oxide dielectric layers with equivalent oxide thicknesses of ~1.4 nm and leakage currents of <1 × 10^-7 A/cm². This is extremely small in comparison with the 1 mA/cm² limit that is permissible for low-power devices.

Gate dielectrics of nitrided silica are currently applied in batch reactors. The wafers are transferred to separate reactors for deposition of doped polysilicon gate electrodes. The dielectric is exposed to air between these two steps before it is capped by the electrode, resulting in the possible formation of extra interface oxide. Air exposure is avoided in the ALAD1N+ process by combining the ALCVD reactor with other tools in a cluster system. The cluster can incorporate pre-cleaning and surface pre-treatment modules to render the wafer more suitable for monolayer deposition.

The migration of boron from polysilicon into the dielectric must be minimized. This problem is being tackled by using materials that have lower boron diffusivity than silica, but which also maximize the dielectric constant. The testing of such materials and their evaluation as gate dielectrics in full CMOS process flows is expected to be completed within the project period.

As feature sizes decrease, interconnect densities must be scaled, so the current six will increase to eight or even 10 soon. This creates problems in the deposition of the barrier and seed layers because the vertical dimensions do not scale as much as lateral ones.

Technology patented by ASM Microchemistry for chemical treatment at up to 400°C is expected to offer a novel way of cleaning damascene structures before metal deposition. The partners predict that solutions will be ready for the manufacture of low-k/damascene structures by the time the project ends, and that they could replace conventional physical vapor deposition and CVD for barrier and seed layer production next year.

ALCVD will also be used to investigate the inter-polysilicon dielectrics used as barrier layers to effect charge retention in non-volatile memories. A two-stage process currently is used with top and bottom electrodes of doped polysilicon added in a separate batch reactor, but this cannot provide adequate performance if the layer thickness is <~13 nm. No alternative is yet available for the 9-11 nm layers required for sub-100 nm chip generations. High-k ALCVD materials could provide a solution, in which case a cluster tool would be developed for deposition of the layers without exposure to air between the steps.

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