NIST-Traceable Pitch Standard Enables CD-SEM Calibration

When a semiconductor manufacturer needs to use an imaging system, whether it be optically based or an atomic force microscope (AFM), it must first ensure that the platform's results will be accurate. This requires that the imaging system's magnification be calibrated. For a CD-SEM, for example, the best way to do this commonly is through the use of a pitch reference, which is a precisely fabricated sample that has a repeating pattern of a known pitch.

As circuit features and dimensions continue getting smaller, calibrating magnification at a higher level becomes even more essential. This, in turn, requires increasingly smaller-pitch-value standards. To this effect, VLSI Standards Inc. (San Jose) has developed a NIST-traceable sample with a 100 nm pitch — called the NanoLattice — specifically designed to cope with the needs of magnification calibration. Another application for the sample is in the verification of the imaging system's linearity. Across a CD-SEM's field of view (FOV), magnification may be different on the screen's left side than on the right side, possibly resulting in distortions. In this case, having a periodic pattern of a known, constant pitch across the FOV enables the user to detect those distortions and perform the necessary scan linearity calibration.

The International Technology Roadmap for Semiconductors (ITRS) requirement for line-edge roughness at the 100 nm node is 3.3 nm 3 σ, measured over a length of line equal to 4× the technology node. The new standard is extremely smooth at the edges and therefore targeted to the 100 nm technology node.

This is significant because, even if a repeating structure is provided as a standard, ragged line edges can make it difficult to locate the line's edge and thereby introduce considerable uncertainty into the calibration. With extremely straight lines, however, it becomes possible to improve the calibration's accuracy.

VLSI’s NanoLattice has a 100 nm pitch that has been designed to meet CD-SEMs’ magnification calibration needs. It can also be used to verify the imaging system’s linearity. (Source: VLSI Standards

A pitch sample was sent to NIST, where it was measured and calibrated using a calibrated AFM that utilizes a interferometric stage for first-principle traceability. That original sample became the prime calibration source and can be employed as a master, enabling other pitch samples to be measured with NIST traceability through a direct comparison using a CD-SEM at VLSI Standards.

As a product, the calibration standard will come with a certificate of NIST traceability and associated uncertainty. According to VLSI, the company has set — and is able to meet — a specification of <1 nm of uncertainty in the traceable measurement. This uncertainty is qualified at a 95% confidence level, according to the ISO Guide to the Expression of Uncertainty in Measurement.

A principal feature of the new standard chip is its configuration. It comes mounted on a 150, 200 or 300 mm silicon wafer that can be loaded and unloaded by automated equipment. The chip is mounted within a recess built into the wafer itself, and the mounting process ensures that the chip's height will be within a specified tolerance of the rest of the wafer's height. This minimizes the possibility that there might be a difference in focus that could affect the calibration.

The user loads the wafer onto the CD-SEM platform and navigates toward the chip standard, using precise alignment marks that have been printed on the wafer to simplify the process's automation. Using pattern recognition, the system finds the location and then navigates to the chip.

CD-SEM systems typically come with a calibration routine where the appropriate magnification and focus are set, and a measurement of pitch is done. Using the information provided on the certificate accompanying the test wafer, the user knows, for example, that the resulting number should be 99.8 nm. If the CD-SEM is out of calibration and does not read within the uncertainty limits of the numbers indicated on the certificate, the user may then decide to change the tool's calibration.

As of this writing, the new standard is in beta testing with a number of major semiconductor manufacturers, as well as a leading tool manufacturer.

For additional information on inspection, measurement and test, go to www.semiconductor.net/imt.