Eliminate CMP Defects by Eliminating CMP

Chemical mechanical planarization (CMP), an enabling technology for copper damascene processing, also suffers from yield-detracting problems of scratching, peeling, dishing and erosion. These issues have become even more pronounced as companies have begun introducing low-k dielectrics with copper. Oxide caps are typically used to firm up a dielectric so that it can withstand CMP, but this mechanical strengthening comes at the cost of a higher effective dielectric constant (k_eff) in the stack. As engineers continue to identify, source and eliminate CMP-related defects, others are looking at alternative planarization approaches that eliminate CMP altogether.

One such approach being investigated by Sony Corp. (Tokyo), TSMC (Hsinchu, Taiwan), and other firms involves electrochemical dissolution of copper films, also called electrochemical polishing (ECP), which is performed by reversing the plating current in an electrochemical deposition (ECD) system. At the IEDM conference in December, Sony revealed an ECP strategy that includes removal of copper complexes using a soft pad and very low wiping pressures, thereby eliminating the stress-induced peeling of low-k dielectrics that often occurs during CMP. Also reported at the conference were TSMC's results of using electropolishing on a 4-level Cu/low-k interconnect device, which demonstrated excellent yield. The process allowed nanometer smoothness and uniform <111> copper texture.

Sony's Soft Polishing Technology and Electrochemical Dissolution simultaneously apply ECP current while removing copper complexes using a soft pad and applied pressure <10× that of CMP. The optimized processes produced erosion and scratch-free damascene interconnects. The researchers achieved removal rates of 8000 Å/min, which is competitive with CMP processes.

The researchers evaluated the process on features 0.20-25 µm wide. The process reduced the step height on a 20 µm line from 5500 Å to <300 Å (3σ). Chemistry was optimized by using several additives to facilitate copper complex formation, copper surface smoothness and increased removal rate. The system also required a new electrode configuration. The use of periodic pulsed-mode operation further reduced copper film roughness and increased planarization. The Sony researchers contend that ECP is a promising replacement for CMP that significantly widens the choices of softer low-k dielectric film that may be suitable for advanced, multilevel interconnects.

TSMC compared a traditional ECD/CMP process with an all-ECP process (no CMP) and a combination ECP/CMP process to determine performance and throughput differences. The group explained that one challenge in developing the electropolishing process lies in processing non-uniform topography from traditional plating processes, which lead to over-polishing in wide trenches and under-polishing in dense areas. As an alternative, TSMC deposited some films by contact plating, a process that tends to produce more planar profiles than traditional ECD, which covers conformally.

TSMC's CMP-free process required only 10,000 Å of copper when deposited by contact plating to fill a 35,000 Å deep trench and achieve global planarization. This process is followed by TaN barrier etching (RIE with F-based gas) and brush Cu cleaning. It requires about a third of the copper and offers twice the throughput of a conventional plating process that requires 38,000 Å of copper to fill the wide trenches and cover field areas. A third approach, the CMP-less process, was accomplished by partial ECP and partial conventional CMP. In each case, the group measured dishing on 120 µm bond pads and erosion on 0.16/0.18 µm (width/ space) dense patterns of 300 × 300 µm area.

The CMP-free process offered twice the throughput and less dishing than ECD/CMP on a 4-layer copper/low-k interconnect structure (Table). Despite significant throughput advantages, the researchers noted that copper film roughness after electrochemical polishing is a key consideration for the CMP-less and CMP-free processes. Surface roughness was reduced by optimizing the current, over which there are three mechanisms of removal — surface limited (0.5-1.5 A), diffusion limited (1.5-4.5 A) and H₂ evolution (over 4.5 A), leading to an RMS of 44 Å. The CMP-free wafers yielded the lowest metal sheet resistance but broader leakage current distribution (still <1 × 10^-8A) than conventionally processed films. Sheet resistance of the CMP-less processes were comparable to conventional at 2.1 µV-cm for 0.16 µm line. The optimized ECP processes produced high yielding via chains and highly <111> texture copper. In a 4-level interconnect, throughput is ~3× that of conventional ECD/CMP processes. Wafer-level testing of a 4 Mb SRAM with 0.13 µm technology produced yields consistently above 85%.

For additional information on yield management, go to www.semiconductor.net/yield.