SoL-Compliant Wafer-Level Package Technologies

A key component of the interconnection hierarchy that will be severely challenged by gigascale integration (GSI) is chip-to-module interconnection integrating a packaged chip into a digital system.¹ A gigascale system-on-a-chip (GSoC) calls for the development of new and cost-effective integrated I/O interconnect solutions using, for example, integrated electrical, optical and rf approaches to meet all the I/O requirements of the sub-50 nm International Technology Roadmap for Semiconductors technology nodes.² Meeting these challenges is essential for the semiconductor industry to transcend known limits on interconnects that would otherwise decelerate or halt the historical rate of progress toward GSI.

In general, power, clock and signal I/O functions will be met by the selective integration of fine-pitch (<30 µm pitch area array) electrical, optical and rf I/O interconnect technologies. These high-density integrated I/O interconnects will be especially important for novel 3-D structures as well as high-current (>400 A) and high-bandwidth (>40 Tb/sec) applications.¹ To investigate the above issues, focus must be given to overcoming long-range and fundamental barriers in chip-to-module interconnects by advancing fine-pitch compliant electrical, optoelectronic and rf interconnections, as well as wafer-level testing and burn-in.

Sea of leads (SoL) is a novel ultrahigh-density packaging technology designed to meet future chip-to-module interconnection needs. Unlike conventional packaging, SoL extends wafer-level batch fabrication of multilevel interconnect networks to include the chip's I/O leads. A SEM micrograph illustrates a portion of an SoL package with 12 x 10³ X-Y-Z-compliant leads/cm² (Fig. 1).³ In-plane and out-of-plane compliance were measured to be >30 µm. While the leads are X-Y-Z axis-compliant, they are short in length and thus exhibit minimal parasitics from dc to 45 GHz. The calculated resistance and inductance of the leads are <25 mΩ and 0.1 nH, respectively.³ Low electrical parasitics are desirable at both low and high frequencies for efficient conductive coupling of power, low power dissipation in the leads and thus low heat generation by the package. The microwave characteristics of SoL were measured at wafer level using a two-port network analyzer with 150 µm coplanar ground-signal-ground (GSG) probes.

1. SEM showing part of an SoL package with 12 x 103 X-Y-Z-compliant chip I/O interconnects distributed across a cm2. In-plane compliance compensates for the CTE mismatch between the chip and the substrate. Out-of-plane compliance is needed during wafer-level testing/burn-in due to non-planarity of testing boards.

Another microwave measurement was made on a fully processed package where the leads were connected in pairs by 100 and 1 µm-thick copper interconnects routed along the wafer surface. The worst case return-loss and insertion-loss for a pair of interconnected leads were measured to be <12 and 1.2 dB, respectively. These measurements include the losses due to the Cu interconnects. Crosstalk between adjacent parallel leads was <30 dB at 45 GHz, and crosstalk between orthogonal leads was ~40 dB. All interconnect structures were ~20 µm wide. All the compliant leads measured were ~110 µm long.

Similar microwave measurements for other packaging technologies have been done. It appears that the SoL measurements reported above compare well to flip-chip packages, widely used in microwave applications. However, the ultrahigh I/O density of SoL can provide an exceptionally high I/O bandwidth that would be difficult to match using alternate packaging technologies. For example, if 8000 leads are assigned as signal I/Os and operated at only 5 GHz, the SoL package shown in Figure 1 can yield an aggregate electrical I/O bandwidth of 40 Tb/(cm²-sec). Also, an SoL package avoids microwave performance degradation caused by underfill, since no underfill is required during assembly. This is in contrast to assembly requirements of flip-chip and BGA packages, where the presence of underfill increases insertion-loss and shifts the return-loss frequency response to lower frequencies.^4,5

2. Micrograph of an embedded optical waveguide and air-gap region within an SoL package.

Next-generation SoL technology will incorporate optical waveguide interconnection to permit global optical clock distribution within high-performance chips. Optical waveguide interconnection allows for planar packaging of a hybrid electrical/optical system in a manner conducive to future heat removal and power supply requirements. In addition, polymer waveguide technologies offer immediate and low-cost compatibility with wafer-level fabrication processes. Minimal redesign of the global distribution would be required with increases in clock frequency, since design of the cross-sectional dimensions of an optical waveguide is independent of the clock frequency. Global propagation of the local clock frequency would be possible, thereby eliminating the need for global clock repeaters. This also permits the removal of cycle-to-cycle jitter from the global clock signal in its delivery to optoelectronic receivers for optical-to-electrical conversion. Finally, optical waveguide clock distribution would allow for enhanced predictability with respect to the arrival time of clock pulses at different optoelectronic receivers, thereby eliminating unexpected components of global distribution skew.⁷

A key feature of the proposed technology is the use of embedded air-gap regions as the upper cladding for optical waveguides. Embedded air-gap cladding regions allow for a maximization in refractive index contrast, Δn, between waveguide core and cladding, and hence permit smaller bending radii and higher waveguide densities due to tighter confinement within the waveguide core. By placing optical waveguides within the package, via blockage concerns are eliminated with respect to waveguide routing, leaving only electrical I/O interconnection to obstruct intra-chip waveguide routing.

3. Schematic of a multilayer probe substrate  with compliant probes

Ultrahigh-I/O-density SoL technology has the potential to revolutionize testability of future GSoCs. Because the die are still in wafer form after packaging, it becomes possible to test multiple packaged die. Multi-die site testing is the first step toward wafer-level test and burn-in. The test time per wafer in multi-die site testing is reduced since the mechanical stepping probe head requires fewer steps to cover an entire wafer.Shorter test time per wafer translates to reduced test costs.

4. SEM of a single compliant probe consisting of an "S"-shaped lead, and four prism-shaped metal probe tips. Thousands of probes like this one can be fabricated simultaneously on the probe substrate.

The benefits of ultrahigh-density WLP technology in terms of testing can be realized only with use of a compatible probe substrate to interface the SoL DUT with external test equipment. A novel high-density compliant probe technology has been conceived to achieve this task. The probes can be batch-fabricated for use in various probe card configurations to provide a reliable and high-speed interface between high-pin-count packages on one side and test equipment on the other side.¹¹ A schematic of a simple multilayered probe substrate is shown in Figure 3. The compliant probes themselves are a modification of the leads from the current SoL process, and are designed to provide compliance in the X, Y and Z directions. A SEM micrograph of a single compliant probe is shown in Figure 4. The structure consists of an S- shaped lead connected to the substrate through a via on one end and terminated by a circular contact at the other. On top of the circular contact lie four raised prism-shaped contacts with which the solder bumps of the package under test would come in contact. The lead rests on a compliant interposer that has been shown to provide compliance along all three axes.³

When a compliant package is to be probed, it provides further flexibility for better contact. The probes provide all the requisite compliance while contacting a non-compliant package. As the compliant probes are a progeny of the SoL leads, they inherit their high-density, high-bandwidth and low-parasitic characteristics. The compliant probes are fabricated in an area array to match the footprint of the SoL package. This technique can easily be extended to probe multiple die sites of not only WLPs, but of other high-density packages as well.

The use of SoL enhances the tail-end-of-line phase of manufacturing not only by driving down cost, but by increasing the efficiency of testing a GSoC. The compliant probe substrate extends the benefits of SoL by providing a reliable interface between the DUT and the ATE. Probe substrates fit with these high-density, batch-fabricated compliant probes facilitate the first steps toward massively parallel test methods and achieving full wafer contact and test capabilities.