Tailoring Tracks for Spin-on Dielectrics

Roughly based on their photoresist predecessors, spin-on dielectric (SOD) tracks can take advantage of the reliability of established platforms, wafer handling and WIP management systems. With altered spin-coat (Fig. 1) and baking plates, where SOD tracks differ most is in the final curing step, which requires much higher temperatures (~450°C) relative to resist post-exposure bakes (~130°C). One can liken the relationship between resist thickness uniformity and CD control to the correlation between SOD coating and curing uniformity to stability of the film's dielectric constant, k.

Perhaps the most significant challenge track system and SOD material suppliers face is delivering integrated process solutions to compete with integrated CVD solutions. Over the past 18 months, material offerings have also expanded. Whereas originally there were low-k spin-on intermetal dielectrics that had to be combined with CVD etch stops and barriers, material suppliers now provide films for many layers, which will ultimately allow all-spin-on solutions. Such approaches would obviously provide tremendous cost advantages over combined spin-on and CVD dielectric stacks.

"We need to take into account the bigger picture," said Dave Vidusek, marketing manager for spin-on dielectric tracks at Tokyo Electron Ltd. (TEL, Austin, Texas). "We're forming extremely close partnerships with the materials suppliers to deliver a dielectric stack, including etch stop layers and hard masks, that meet the customer's technology needs as well as cost targets." Such integration efforts are essential to SOD's ability to compete with CVD on cost. In 2002, years after the low-k CVD vs. SOD debate began, these dissimilar approaches both remain viable going into the 90 nm device generation (see next month's issue of Semiconductor International for a feature reviewing CVD and spin-on low-k dielectric progress).

1. The spin-coating process for SODs is optimized for uniform coverage across up to 300 mm substrates as well as reduced low-k material volume. (Source: TEL)

2. Design of the SOD track system uses a stacked, vertical configuration to minimize cleanroom footprint. Separate process zones are used for chemical delivery, spin-on coating and thermal treatment. (Source: DNS Electronics)

SOD track platforms are developed around resist tracks that already handle multiple processes. "We used an evolutionary approach to tool platform, using the same ACT 8 and ACT 12 platforms, but with a revolutionary approach when it came to the material requirements themselves, which influenced the coating module design and high-temperature hot plates with oxygen control," Vidusek said.

3. The scan-coating technology scans the wafer to increase coat uniformity and minimize the material run-off that can contaminate the wafer and chamber and lead to higher cost. (Source: TEL)

"Coating uniformity and bake temperature uniformity are the primary technical metrics of track performance, but the demands are less stringent than leading DUV photoresists," Pieczulewski said. Coat uniformity for resists are on the order of <0.5% (3s) of mean thickness while SOD coatings perform well at <3% (3s) of mean thickness.

Ambient control is critically important during spin-coating, baking and curing processes. Most systems limit oxygen exposure levels (<100 ppm) throughout thermal cycling. However, one SOD track user commented on other crucial ambient control issues that directly influence the reproducibility of SOD films. He explained that the track must be designed to continually remove evolved gases from the spin cup and hot plate areas. If not controlled, these gases can cause secondary reactions, wafer defects and thickness variations, as well as tool downtime. He added that in-line metrology is also necessary to monitor thickness variations.

4. A 200 mm wafer enters the Instacure module, which provides ramp-up to 450°C, low-oxygen curing (<50 ppm) and ramp-down (using N2) for controlled curing of SOD films in a ~4 min cycle. (Source: FSI International)

The first curing steps were performed in vertical furnaces, which many films still require. Some equipment manufacturers offer track systems that can be interfaced with furnaces, while most offer some type of in-line cure, usually using high-temperature hot plates. One exception is FSI International's (Chaska, Minn.) Instacure module (Fig. 4), which is more like a thermal CVD chamber capable of processing up to 450°C. Other options for curing include fast-ramp furnaces, RTP or fast-ramp plasma furnaces.

According to Pieczulewski, achieving full wafer cure is the market entry requirement for the track system or furnace supplier -- so companies compete from the standpoint of throughput. Since curing time is material-dependent, chamber purging, ramp-up and cooling steps most affect throughput, Wong explained.

While the hot plate cure may work for most of the current-generation, non-porous low-ks, there is some question as to whether pore generation can successfully be achieved on a hot plate. For these ultralow-k (<2.2) materials, it may be necessary to stick with furnace cures or use plasma processing, the latter of which is being developed for both JSR's and Dow Corning's materials. For instance, Axcelis Technologies (Beverly, Mass.) partnered with Dow Corning to provide a plasma process, followed by UV cure and RTP to provide rapid curing of XLK porous low-k (~2.2) material. However, despite the variety of approaches being pursued, the optimal ultralow-k material would deliver stable, uniform porosity in the as-deposited film.

Dan Williams, technical marketing manager for FSI's spin-on dielectric systems, explained that initial SOD approaches were going to require more extensive processing changes on the cluster to provide, for instance, uniform porosity in the film. The materials suppliers, however, have made strides in the chemistries that are less demanding on the curing process and have increased the process latitude.

Many factors affect the SOD cost of ownership, including track system cost, material cost (which are comparable with leading-edge KrF and ArF resists), track system throughput, handling requirements and other factors. Because of the high material cost, dispense volume has been driven down considerably. For instance, DNS optimized the coating cycle to include two stages so that only 1 mL of SiLK resin is required to uniformly coat a 300 mm wafer.

"The motivation for single-wafer SOD cures is two-fold -- productivity and 300 mm wafer processing," Pieczulewski said. Typically, the long vertical furnace curing step (usually 60 min) has been the bottleneck to the SOD process. "A track tool with multiple low-oxygen, hot bake plates can continuously process wafers as nearly twice the throughput."

Larry Wagner, president of FSI's Microlithography Division, described the architecture of the company's tool: "We utilize a central robot for handling and can populate multiple modules of each type around the robot. On the Calypso system, you might have two stacked spin modules with four coaters, a couple of bake modules with up to 14 bake and chill stations, and three Instacure modules with up to nine curing stations, yielding a throughput of 80 wph.

Semix's Vortex platform has developed several track systems capable of various process flows and post-curing configurations, including integrated furnace cures. TEL, which offers both vertical-furnace-based cures as well as high-temperature hot plate curing, developed a track system that can accommodate up to eight curing hot plates and achieves a throughput of =65 wph, according to Vidusek.

FSI's Williams warns that, in this critical time between pilot line and volume production, there may be some modifications to the hardware pertaining to reliability. "We have a good handle on the performance specifications, but within the next 18 months, as IC companies begin to run production volumes, they may encounter opportunities for equipment enhancements with exhaust management or effluent drains, for instance, which were not apparent during development and pilot line production."

While track companies continue to make enhancements to improve cost of ownership, Williams explained that perhaps a more relevant factor than CoO is the project risk involved in switching to a spin-on dielectric material. "Timing is critical. The complete integration of an SOD low-k solution is key to its acceptance in the device architecture. CoO alone is really not enough to determine the technology of choice," he said.

The timing for using low-k dielectrics in production devices is a moving target. Different companies are choosing different technology nodes for making the crossover from CVD to SODs. In general, the use of low-k dielectrics, CVD or spin-on, has been pushed out at least two device generations for some companies. At the same time, the industry is beginning its full-scale push to 300 mm. The near-simultaneous conversions to copper, low-k dielectrics and 300 mm, combined with the market downturn, have created an extremely challenging environment for materials and tool suppliers, Wong commented. Herein lies the value of industry partnerships, giving tool and material suppliers a more exact sense of timeline from the IC manufacturers.

Vidusek also commented on the years of experience that already exist in the fab regarding spin-coating technology. "One side that people don't always realize is that SOD is not a brand new technology -- it's traditionally an unfamiliar technology to the thin-film CVD technology group in the fab." He added that the fab leadership is the catalyst that promotes effective transfer of the many years of learning from photoresist processing to the SOD process group.