300 mm, New Materials Transform Processing and Metrology

Operationally, 300 mm is not too different from 200 mm and has not changed how chips are made. However, it and new materials are reshuffling the importance of the fab's technologies. Metrology is an example. The need to more closely monitor the wafer has escalated its importance. It is now the early warning system that alerts that something is wrong, before the product is processed and packaged (Fig. 1). New materials, smaller dimensions and lithography — all precariously balanced on a large wafer — are plunging the industry into unchartered waters.

"There are surface preparation complications for 300 mm. Initially, we thought that 300 mm production would be done at 0.13 µm," said Rol Yalamanchili, director of process development at SCP Global Technologies (Boise, Idaho). "Now we're focusing our efforts on surface preparation solutions for <0.10 µm technologies."

"We all committed to 300 mm 18 months ago, but the effort required much more than a scale-up," said Chris Moran, vice president of corporate marketing for Applied Materials (Santa Clara, Calif.). "With the continuously changing requirements that span materials, linewidths, metrology and automation, it's taken time to get to this point, where we're performing well."

Were the industry to be mapped, lithography would occupy the unexplored, blank areas over which medieval chartmakers inked the warning, "Here Be Dragons." The question now is what happens at 157 nm. Although R&D will not slow down when the benefits are clear, 300 mm's lesson is that, if costs skyrocket, technologies are questioned. Lithography is entering this risk area and must go to vacuum-based optics or other technologies that may completely alter it. "Customers want a 130 nm production tool now, to do 0.10 µm in volume the following year," said Jim Greeneich, vice president of strategic marketing at ASML. "Whether doing 200 or 300 mm, logic and fab people are buying 193 nm tools to do 0.10 µm and simultaneously run 193 nm production."

For 300 mm to be economical at 0.10 µm and below, yield is essential. Here, metrology plays a leading role. "We do integrated metrology on the tool," said Greeneich. "As we expose one wafer on our double stage, we do metrology on the other. You do focus mapping or alignment on any site on the wafer, improving yield on every field to the edge."

1. The move to 300 mm is not just a change in wafer size. The convergence of copper and low-k dielectrics, more deposition layers, and additional process steps require that other technologies like metrology, clean and data mining keep up. (Source: SCP Global)

Projection lithography opens packaging applications, said Steven Kaye, director of product marketing for advanced packaging applications at Ultratech Stepper (San Jose). "Everyone's interested in 300 mm wafer bumping. An issue everybody's dealing with is 300 mm automation requirements — meeting software and hardware communications protocols. Many equipment sets are unprepared to handle FOUPs, for instance. This is changing, because if you're sending your 300 mm wafers to be packaged, you want them to remain in the FOUP. Packaging toolsets must handle that automation level."

Lithography is becoming a packaging process mainstay, as manufacturers add it to do bump packaging. As Kaye puts it, "High-density package, multi-level substrates, system-in-package devices, and stacked devices are becoming mainstream. In two years, 5 µm or less linewidths will be needed on substrates."

Compared to past transitions — i-line to 248 nm, 248 nm to 193 nm — resist technology is progressing quickly, raising concerns whether materials will be available at the appropriate maturity level. "The industry is going to 157 nm, and looking at a resist implemented with a low k₁ factor," said Greeneich. "With 157 nm, there isn't a fielded tool yet with which to determine resist process issues." Once 193 nm is implemented, there will be an effort to push it and delay 157's implementation.

EUV will be a tremendous challenge for lithography. Moving into the vacuum world is difficult because of the necessary high-speed motions and stages — it is not static processing. Plus everything changes: The optics are new, working with vacuum is new, and material issues are unclear. EUV requires mirrors — more exacting polishing requirements. Costs to bring it to market will be outrageous.

Metrology's value depends on what is done with its data. "We're taking the industry beyond its traditional data collection and evaluation mode by linking metrology, often integrated on the tools themselves, with sophisticated software that can provide automation defect analysis and suggest root causes of defect issues," said Moran. "Building on the process and tool data from our integration centers and from users, we're supplying defect detection solutions that don't just identify problems, but tie defect data to process techniques to improve yield."

On the inspection side, most OEMs are satisfied. "We meet 300 mm needs with a broad suite of optical and e-beam inspection tools," said Pete Nunan, vice president, yield technology services group at KLA-Tencor (San Jose). "Record improvements in optical inspection — shorter wavelengths and algorithm enhancements — have been delivered. They're complemented with advanced e-beam inspection; these tools are key to finding hidden issues at sufficient throughput. This takes place as we go from 0.18 to 0.13 µm. Recently, a major foundry was quoted as confirming that they had reliability problems with 0.13 µm copper. Obviously, foundries are at the bleeding edge, and learning that you don't get shippable product the day that you plug it in, which was the model in the past." Clearly, if R&D gets working chips at 0.13 µm it is not the same as churning them out at a 10,000 wafer-a-week level. Capability is not capacity, particularly since underlying flaws remain undiscovered until larger volumes are reached.

Steven Berger, CTO for FEI (Hillsboro, Ore.), views 300 mm as an adjunct to structure size reduction. "CDs are shrinking and optical lithography moving to shorter wavelengths and better resist materials, higher NAs," he said. "Simultaneously, process margins must be maintained to give manufacturing flexibility. Over time, we've brought in high-contrast resists with 248 nm lithography and higher NAs. This kept manufacturing margins up. We've moved to reticle enhancement techniques with similar results."

Berger pointed out that additional process control is needed to maintain acceptable manufacturing margins. FEI has developed structural process management capabilities, such as cross-sectioning, to determine what happens within a device's structure. "With 300 mm, throughput demands this must be done without the high cost of breaking wafers. Profile measurements are important in areas such as resist, shallow trench isolation, and dual-damascene structures. Getting to root cause requires three-dimensional capability. By using combined FIB/SEM systems, materials can be cross-sectioned, imaged, and measured inside the fab, providing fast time to results."

"Due to the electron charging effect that not only limits measurement accuracy and repeatability, but can also damage the measurement area, current CD-SEM metrology capability is becoming a bottleneck in providing accurate and repeatable CD measurements for advanced technology processing," said Wenge Yang, director, product marketing at Timbre Technologies (Fremont, Calif.). He added that the problem is exacerbated with 300 mm, due to higher wafer cost, increased sampling rate requirements, the need for APC, and the requirement to correlate CD and profile measurements to critical process parameters and adjust processing conditions in real time.

Yang views scatterometry as a solution. "Some of scatterometry's major benefits include instrument precision improvement to under 1 nm, vs. 2 to 3 nm on a CD-SEM," he said. "It also provides a compact metrology solution that can be integrated to process equipment, which matches process tool speed up to 120 wph. Also, the technique generates full profile measurements instead of single CD results."

2. Metrology for the 300 mm wafer can affect sampling density or throughput. With as many as 2.5 times more chips, it does not appear that the same areal density of metrology measurements can be maintained, unless the manufacturer is willing to reduce throughput by 60%. Lower sampling or higher performance by metrology systems will doubtless be the answer. (Source: Rudolph Technologies)

The increased size of a 300 mm wafer presents a metrology dilemma that affects either sampling density or throughput (Fig. 2). A 300 mm wafer has 2.25 times more surface area than its 200 mm counterpart and, depending on die positioning, can have approximately 2.5 times more chips. "Initially, people talked about maintaining the same areal density of metrology measurement," recalled George Collins, vice president of marketing at Rudolph Technologies (Flanders, N.J.). "That would require 2.5 times more measurements per wafer. If measurement time per site isn't increased, throughput would drop 60%."

Most are unwilling to take that magnitude of throughput hit. In fact, many manufacturers who performed 5-point sampling at 200 mm are considering performing 9-point sampling on a 300 mm wafer. This represents a 30% drop in 300 mm sampling density, and still cuts throughout almost in half. "Lower sampling density puts yield and 300 mm's economic benefits at risk," said Collins, "so manufacturers are demanding higher throughput from their metrology suppliers."

Nobody is shipping low-k with copper — it is done with FSG or undoped silicon glass. Soon, low-k must be integrated and ramped into production. That, combined with lithography complications, starting with mask-making and inspection, and contact printing are tall orders. "Just the seemingly straightforward contact printing probably is, after gate, photolithography's next big challenge," said Nunan, adding that the entire gate area is APC-driven. "Optimal transistors require tighter dimensional control over gate formation, driving the industry toward advanced APC. APC provides better distribution and data needed for gate dimensions. As for contacts, minor reticle dimension variations on a contact blow up into missing contacts on the wafer. This process window is very tight." KLA has reticle inspection tools that detect differences in contact size — solving this problem before the reticles get to the fab — and inline inspection tools that detect sub-size contacts or vias — defects that can lead to potential "resistive" vias in copper processing.

"We're contending with a new equipment set, a new wafer size, shrinking geometries, and more potential for material changes throughout the whole flow," said Dave Hemker, vice president of new product development, at Lam Research (Fremont, Calif.). "If you consider FEOL and talk about shrinks, you're concerned about CDs, which drive everything. In each device generation, the easiest problem is addressed first. Recently this has been gate lengths, because we've been able to do a trim etch, and litho adjustments. Now, metrology becomes important because <100 nm gate lengths are common, and a few nanometers' variation make a difference." Since SiO₂ cannot be made less than an atom thick and that thickness is leaky, the search is on for different gate materials, and the long progression of high-k gate materials is being trimmed. There is tantalum pentoxide, an intermediate solution that may or may not make it into volume production, and hafnium and zirconium oxide, which show promise.

"Integration issues are crucial and device manufacturers must plan with OEMs, not independently, if they expect to make world-class products," said Hemker. "This way, we both keep ahead of the curve."

The move to 193 nm resist is changing the flow's steps. Issues result because it is less robust and laid in thinner layers than 248 nm resist. This causes problems for etch and CD control, because if the resist is unstable it thins vertically. However, this is more of an issue if the lateral dimension — the roughness, waviness, the actual CD's integrity — changes during processing.

Low-k is the BEOL issue. OEMs are looking at materials with km2.0, both in etch and CMP — specifically porous materials. "On etch, we're looking at how etch byproducts affect materials and k values," said Hemker. "If there are pores, some of the etch material will deposit there. Should we tailor the material to make it easily cleaned, or adjust the process to minimize the effect? Also, what's the impact on the barrier deposition on subsequent steps? Etch is not isolated."

"For me, 300 mm means low-k dielectrics," said Andy Noakes, CVD product marketing manager for Trikon Technologies (Newport, U.K.) "I don't see many equipment, hardware and process transfer challenges. We've already moved our low-k fill technology to 300 mm. Our copper damascene technologies are being developed at 300 mm."

Trikon has an available off-the-shelf option with a k=2.2, and claims extendibility to 1.8. "This year we'll productionize our platform for 90 and 65 nm with k=2.2, and work on the basic characterization of our 1.8 material, including single damascene integration," said Noakes. "The 65 nm extension will probably require a low-k silicon carbide, for etch stop, hard mask or diffusion barrier. We already have a k~3.0 SiC material in development, which is compatible with our k=2.2 film and will give compliance with the ITRS k_eff for 65 nm."

Low-k material adoption could be more aggressive if integration were easier. "This is true with porous low-k materials," Noakes said. "Here you run into problems, particularly with cleaning, after etch, and metal coverage over the porous material for the barrier, and also CMP." Presently, the industry equates ultralow-k dielectrics with spin-on technology. "Not true," said Noakes. "CVD low-k doesn't stop at 130 nm. CVD is the industry's preferred choice for IMD, and can go to 45 nm."

"We're ready for the 300 mm ramp," said Wilbert van den Hoek, CTO and executive vice president of integration and advanced development at Novellus Systems (San Jose). "Going to a silicon oxycarbide low-k material poses real integration challenges for our customers (Table). Virtually everybody has chosen FSG as the low-cost, high-volume production solution for IMD at 0.13 µm, and is talking about using a real low-k (<3.0) material for high-performance pilot production. The 0.10 µm technology node will be low-k's first production node." Low-k will influence technology choices, at both the 100 and 70 nm nodes. Metallization selections will be dependent on the low-k choice, as will CMP solutions.

"For us," said van den Hoek, "the good news is that PECVD won the <3.0 film battle with spin-on. PECVD films are easier to integrate." The industry faces integration issues with k<3.0 films, including CMP problems, photoresist poisoning issues, adhesion complications, etc. This will not improve with k<2.5 films. "CMP may have to be abandoned for electropolish. Low-k choices will drive the interconnect arena."

Low-k material choice (because of sidewall roughness, etch profiles, undercuttings of barrier layers associated with etch, etc.) will determine whether PVD or CVD will be the technology for barrier and seed deposition. Whether it is CVD or ALD will also be similarly determined. "If we're going to truly porous materials that allow gas diffusion through the film, conventional ALD will have compatibility challenges," said van den Hoek, "because of its tendency to coat the inside of the pores of these low-k materials."

When the physical dimensions of the interconnect become similar to the mean-free path of electrons in the copper, the copper's utility as interconnect becomes questionable. This occurs when the minimum width of the line reaches about 50 nm. It is unclear which interconnect solution will be available to maintain an interconnect structure with the resistivity of 2 µm/cm.

"There's no consensus on where the industry is heading regarding high-k dielectric materials," said SCP's Yalamanchili. SCP is waiting for a consensus on materials to focus its surface preparation technology development efforts. "Material choice changes surface preparation," he said. SCP is considering several possibilities for improved surface passivation through the integration of processes capable of controlling the interfacial aspects for high-k materials.

The removal of smaller particles — 65 nm is being discussed — associated with smaller geometries is another problem for surface preparation providers. "Removal of this size particles without damage to the substrate material isn't trivial," said Yalamanchili. "We cannot rely on megasonics, because with extremely high frequencies — 3-4 MHz — there are device damage and megasonic hardware issues; in addition, reliable metrology to measure such small sizes is unavailable."

The cleaning and rinsing of high-ratio features poses headaches. "Drying technology plays a major role in meeting this challenge. Currently available IPA drying technologies can be broadly classified into two categories: some form of surface tension gradient drying and vapor condensation drying. Calculations and results show weaknesses in surface tension gradient drying technology for high-aspect-ratio features due to lost or altered meniscus at these features. Vapor condensation-type dryers appear to perform better with very high-aspect-ratio features.

Some current wet processes should be good for up to 80 nm. Beyond, there are water surface tension limitations. "We're looking at supercritical fluid processing," said Yalamanchili, "such as CO₂, which has nearly zero surface tension and can reach high-aspect-ratio features for effective surface preparation.

As Moore's Law proceeds on its steep slope, some reflect that we may be approaching the limit not of engineering, but economic capabilities. It may not be fundamental limits that derail us, but the expense of coping with them. Maintaining an economic manufacturing capability while making a profit will prove problematic. It might accelerate the move to the foundry model, where residing pools of process and design experts can cope with these problems.