TI Unveils 90 nm Process

Texas Instruments (TI, Dallas) took the wraps off its next-generation 90 nm process technology, which features transistors with gate lengths as small as 37 nm. The company made the announcement as part of its introduction of new ASIC libraries and design kits based on the 90 nm process. Although the 90 nm process is not expected to be in production until 2004, which is in accordance with the latest revision of the International Technology Roadmap for Semiconductors (ITRS), it is unlikely that changes will be made to the process now that it has been announced.

The company recently produced the first integrated silicon using the process, although it was based on larger gate lengths of 52 nm. The process is expected to go through a prototyping phase early next year, followed by qualification in the second half of 2003, initial production ramp in 4Q03 and high-volume production in early 2004.

"There's a level of confidence that we have this capability, both from a standpoint of process and from a completeness of design tools and models," said Hans Stork, vice president of silicon technology research and development. "People can start their designs with it, and they will get products when they need them."

The 90 nm process includes up to nine layers of copper interconnect integrated with a low-k dielectric, organosilicate glass (OSG). TI decided to use the CVD-deposited Coral material developed by Novellus, which has a dielectric constant of 2.8. "We have certainly evaluated other materials along the way, but the choice to use Coral took place in the middle of last year," Stork said.

1. Six-level metal interconnect cross section of TI’s 90 nm process, showing integration of copper, with OSG film dielectric on metal levels 1 through 4, and FSG film on metal levels 5 and 6. (Source: Texas Instruments)

2. A close-up of Figure 1, with specific layers defined. (Source: Texas Instruments)

For the gate dielectric materials, TI will stay with a plasma-nitrided oxide (PNO) for the core transistors, which will be scaled to 1.3 nm for the first time. "We've been able to get several learning cycles already on this nitrided oxide," he explained. In terms of the more exotic high-k gate dielectrics, such as hafnium or zirconium silicates or oxides, issues related to process integration, mobility, threshold voltages and reliability have yet to be resolved, he added. "We have some efforts in that area as well and are very well along the learning curve, but we don't expect it to be ready for this generation."

When asked if it might be possible for changes to the process to be made, considering it won't be in production until 2004, Stork said it was unlikely. "It would really have to be a breakthrough in the next six months, and a really significant breakthrough for that to be a possibility."

TI's 90 nm process is being developed for both 200 and 300 mm production. Development work is now underway in the 200 mm Kilby wafer fab, and volume production will be in the 300 mm DMOS6 wafer fab in Dallas, said Peter Rickert, director of process technology development and TI fellow. Based on the company's experience with its sub-0.13 µm process, which is in qualification now, Stork said he did not expect there to be much of a delay between when the process would be available in 300 mm after 200 mm. "There might be a quarter difference but not much more," he said.

	3. Transistor cross section of TI’s aggressive 37 nm transistor, to be used in microprocessor-class applications. (Source: Texas Instruments)

For additional information on wafer processing, go to www.semiconductor.net/wafer