John K. Kibarian, PDF Solutions President and CEO

John Kibarian is a founder of PDF Solutions (San Jose), and has served as president since November 1991 and CEO since July 2000. He received a bachelor's degree, master's degree and Ph.D. in electrochemical engineering from Carnegie Mellon University.

SI: What is PDF's product niche in yield management?

Kibarian: We examine and model design and process interactions on a fundamental basis so that IC companies can accelerate yield learning rates on new technologies, processes and designs. Our process/design integration infrastructure allows us to fully characterize the state of the process, and then we build a set of models that tell us how the design interacts with that particular process.

SI: Can you describe this infrastructure?

Kibarian: We develop a library of yield loss phenomena for each technology node and directly map the product to the test structures to yield loss. Specific test vehicles are semicustomized or configured for a set of conditions, and together with our yield analysis software and our models, we produce a yield impact matrix.

SI: How does this differ from other industry approaches?

	John Kibarian (Source: PDF Solutions)

At the 0.13 µm node, the traditional approach becomes very expensive. The factory is over a billion dollars, the mask sets are close to a million dollars and every one of those iterations is lengthy and expensive. In addition, while you work through all those problems on one product, the next product comes in and it has a different set of yield issues. When you eventually get to the 100th product, the bugs are worked out, but it's a slow, painful process.

SI: How does your company improve on this process?

Kibarian: Of course, there are still the negotiations between the process and design groups to generate the design rules — but we look at the intellectual property that's used for this technology node, the designs from the last technology node, and try to understand how a customer's designs actually use the process. For instance, at the via level, we try to identify every environmental condition that will cause a via to yield differently. We form a design of experiments around those conditions, on a test mask that's designed specifically to look at yield loss for each of the via layers. We'll also have one for metal, contacts, poly, etc., all looking at the design and process interactions on a fundamental basis.

SI: How does this tie in with design?

Kibarian: After we characterize the state of the process, we build a set of models that tell us how the designs interact with that process. We can look at any individual design and see what elements it uses and in what frequency, and run it through the models. Then we have yield loss by process module and by design block, down through to design elements. From that data we can build a Pareto for that module for all the yield loss effects. This is a yield loss Pareto before the design ever hits manufacturing.

SI: How many customers are using this?

Kibarian: Our first engagement was at the 0.25 µm node; we've done quite a number of projects at 0.18 µm; and are in the process of implementing 0.13 µm and 0.10 µm processes with several customers.

SI: Why do semiconductor companies need to outsource process and design integration?

Kibarian: The truth is, everybody's design rules are a little different, their layout densities are different, runner lengths are different, and there's a whole set of conditions that vary from one manufacturer to another. For our characterization vehicles to be optimally effective, they have to target the defect problems specific to a process or product. The characterization vehicles are short flows, so the customer can get very good insight into the yield problems from a single lot of wafers.

SI: How do you implement solutions at the customer site?

Kibarian: A team of six to eight engineers take a comprehensive toolkit to our clients with a variety of characterization vehicles and software. The project team works directly with the customer and reports to a core team that develops and modifies the characterization vehicles. With the very short feedback between our development groups, we quickly assess what works and what doesn't so that improvements can be made quickly.

For additional information on yield management, go to www.semiconductor.net/yield