Evaluating Device Parameters Decreases Needless Mask Rejection

The industry can certainly agree that photomasks are not the commodity items they once were. Simply looking at the price tags of some of the most complex masks in use today will tell you that. With the increasing complexity of resolution enhancement techniques (RETs), and the rising costs that go with it, discussions have turned from mask defects to printable mask defects. After all, it's not cost-effective anymore to trash or even try to repair every mask that has a defect if the error won't even appear on the printed wafer.

Researchers at Cypress Semiconductor (San Jose), working in conjunction with Numerical Technologies Inc. (San Jose) and Sequoia Design Systems (Woodside, Calif.), have taken this concept a step further. In a paper prepared for Interface 2001 (which was scheduled for November, but was cancelled), they detailed the notion of evaluating the impact of mask defects on device parameters. One aspect of the argument for such measures is that the sizes of legible RET mask features are in the range of minimum detectable defects. Assessing defects by their size and location, therefore, is no longer feasible.

Using simulated transistor characteristics, this two-stage procedure defines the silicon image and identifies the defects that actually degrade device characteristics beyond the limits specified for the device. The method identifies electrical signatures of defects based on their type, size and location. It is based on key parameters such as transistor drive or leakage current, and makes a direct correlation between mask defects and transistor current.

Although some of today's defect qualification tools can already identify defect location with respect to other layers (enabling the evaluation of defect impact on device parameters), the typical criterion used is based on CD variation. In this scenario, incorrect disposition could translate into disqualifying or repairing a potentially good plate.

The proposed evaluation technique adds a disposition criterion to a typical mask writing and acceptance flow, allowing the change of transistor parameters to within a given range. Although this adds complexity to the process flow, this complexity would be offset by a more accurate qualification of defects, the authors noted.

The researchers used the modified process flow to evaluate the impact of chrome defects on MOSFET characteristics for a very dense layout of an SRAM cell for 120 nm technology. Two basic types of defects — potentially the basis for plate rejection — are chrome protrusion and intrusion. Depending on their locations with respect to the FET area, as well as their depth and length, these defects can cause variation in the transistor I_on and I_off. The researchers calculated these parameters by performing statistical analysis of the gate length. They simulated silicon images assuming a 193 nm stepper with annular illumination, basing the models for I_on and I_off on 120 nm NMOS data.

In the automated MOSFET analysis process, the channel is first divided into several parallel sections so that its length can be treated as uniform over each section's width. Discrete parameters are then calculated for each section, and individual I_on and I_off values are extracted. Statistical analysis of the extracted data produces their integrated values for the entire device. Experimental analysis showed that, as expected, defects located outside the channel area have only minimal impact on gate CD, barely changing device characteristics. Simulations also showed that intrusions affect the silicon image more strongly than extrusions.

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