Packaging's Crystal Ball: The 2001 ITRS Roadmap

Technological advances in semiconductor production are advancing faster than they can be predicted. The latest update to the International Technology Roadmap for Semiconductors (ITRS) was released in late November 2001 and continues to show "roadmap acceleration." For example, in 1999 the roadmap predicted transistor channel lengths would be 25 nm by 2013. The latest prediction is to achieve this channel length in 2007. This might mean that the already frightening predictions of packaging requirements will be exceeded by real parts in the coming years.

Since 1992, the Semiconductor Industry Association (SIA) has coordinated the effort to explore where semiconductor technology will be over the next 15 years, bringing together a consensus of more than 800 industry experts.

The ITRS offers 10 primary drivers for packaging technologies: cost per pin, chip size, power, voltage, pin count, thickness, on- and off-chip clock frequency, junction and ambient temperatures. Since it is difficult to generalize across all applications, requirements and solutions are divided among six categories of chips: low cost, handheld, cost performance, high performance, harsh and memory.

Cost will be a primary driver across all applications. For example, the cost-per-pin targets over the next two years are low cost, 0.25-0.56 cents/pin; cost performance, 0.66-1.17 cents/pin; high performance, 1.88 cents/pin; memory, 0.30-1.14 cents/pin.

Because the pin count is predicted to increase faster than the cost-per-pin erosion, the total packaging costs may actually increase over the next seven years.

The predicted maximum pin count off the package for these four categories is shown in the Figure. The prediction of >2000 I/O for next year is close to the mark for a number of network processor and ASIC parts with >100 million transistors. Of course, the off-chip I/O will be significantly higher than the off-package I/O.

	Predicted package pin count for four classes of applications. (Source: 2001 ITRS)

Flip-chip technology is a key requirement for higher-pin-count chips. Enabling this feature will require lower-cost wafer bumping and under-bump metalization (UMB) compatible with on-chip copper metalization and low-k dielectrics. Bump pitches are predicted to decrease from the 160 µm of today to tighter than 70 µm over the next 15 years.

System-in-a-package (SiP) is the preferred term to describe an enhanced functionality module with one or more bare die and possibly passives in a single-chip package. Included in this description are stacked chips. With this definition, SiPs are the fourth wave of packaging innovation. The first three are through-hole technology, surface-mount technology, and array packaging such as flip-chip, BGA and CSP.

In addition to the obvious advantages of SiP over system-on-a-chip (SoC) — such as higher functional density with stacked chips, integration of large passives and ability to utilize the most cost-effective silicon combinations — the ITRS offers reduced cycle time as an important driver. "From design, characterization to manufacturing could be as short as 3-4 months while a SoC would take much longer. The cycle time reduction is why the SiP will continue to play a critical role in component packaging and system integration."

One of the roadmap's most important recommendations is the growing need for chip/package/system co-design. "Package designs no longer can be made independently of the chip and system: they must be considered concurrently in a system level approach to minimize sub-optimization." The harmonic convergence of shrinking design cycle times and higher-performance parts pushing the electrical, thermal and reliability envelopes, with greater complexity, will require design tools that integrate system-level modeling and simulation and data transfer between the chip, package and board design environments.

Since the first roadmap was released 10 years ago, the predictions of where the industry will be 15 years out have proved too conservative. If this trend continues to hold, and IC technology advances at an ever more rapid pace, then, to paraphrase what the Red Queen said to Alice, packaging technology will have to run faster and faster just to stay in the same place.

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