Reflecting on Resists
Laura Peters, Senior Editor -- Semiconductor International, 2/1/2002
I was first introduced to photoresist technology in college, during a semiconductor internship that involved optimizing the coating parameters on a spin coater using polymethylmethacrylate (PMMA) e-beam resist. Later, I worked for a short time at AT&T Microelectronics as a quality engineer. I became familiar with problems of resist rework, residual photoresist and vias that did not open.
When I was hired on to Semiconductor International, one of the first articles I wrote covered i-line and g-line (436 nm) resists that were amazingly going to deliver sub-0.5 µm features. At that time (early 1992), resist suppliers were extending the performance of i-line and g-line resists by formulating solutions for specific layers, while the industry had only begun to investigate resolution enhancements that could allow further scaling of IC features. Researchers and engineers were developing chemically amplified resists, and wondered whether these resists would be extendible down to future lithography generations. Just two years before the introduction of the first SIA Roadmap, what later became known as the "red brick wall" was at roughly a quarter micron. Imaging features much smaller than the wavelength of light used to pattern them seemed like a pipe dream.
Lithographers and resist suppliers today can look back on those times and realize how much simpler things were then. Ten years later, we live in a different world. Resist development costs have skyrocketed and each new lithography wavelength is requiring totally new polymer platforms that take a lot of time to characterize and understand — much more time than is allotted by the aggressive scaling of feature dimensions. The ample process windows of yesteryear — like a 1.2 µm depth of focus (DOF) on a 0.8 line/space pattern and k1 values of 0.8 — are history. Back then it seemed like anything under 1 µm DOF would not prove sufficient to allow for exposure dose variations, stage alignment control, resist thickness variations, and all the other factors that eat up the lithography budget.
In today's competitive environment, subwavelength lithography has become a reality thanks to many hours of research and engineering into photoresist formulations, high-NA lenses, scanner technology, reticle advances and etching processes. Phase-shift masks effectively added another optical element to the lithographer's toolkit. Amazingly, 200 nm isolated lines can be patterned using 365 nm light. A "livable" DOF value on 150 nm 1:1 line/spaces might be 0.4 µm using 0.8 NA KrF scanners and ~400 nm resist. At a combined scanner/track cost of about $10M, together with all the metrology tools for sub-200 nm characterization, it is astonishing that any company can afford subwavelength lithography.
It is the industry partnerships that have allowed such rapid advancement in lithography, and therefore advanced semiconductor devices that follow a rate of progress that exceeds Moore's Law. From the standpoint of cost, resist suppliers, many of which are backed by large corporations, typically partner closely with one or two IC companies in true partnerships.
Pre-competitive research is a reality at such institutions as International SEMATECH, IMEC and SELETE. A shining example is the recent development of 157 nm photoresist platforms at SEMATECH and five U.S. universities, including the University of California at Berkeley, Caltech, the University of Texas at Austin, Clemson University and Cornell University. This unprecedented collaboration resulted in a commercial resist for 157 nm patterning in only about three years, with many more developments to come soon.
157 nm lithography, which must be brought into the fabs in four to five years, requires continual breakthroughs if the technology is going to meet the aggressive insertion date of the 65 nm node. Up against necessary conditions of vacuum processing, CaF2 supply and quality issues, lack of a suitable pellicle material and the need for production-worthy photoresists, it makes sense to pool resources on the fundamental level, reserving IP positions for the specialized materials and technologies that will follow.
