Fabricating 90 nm Devices by 2004

Intense acceleration of industry roadmaps is expected to lead to the fabrication of high-performance devices with 90 nm DRAM half-pitch and 37 nm microprocessor gate lengths by the end of 2004, and perhaps even in 2003. This acceleration has come at a cost, however, as less time between device generations gives limited time to prove the reliability of new materials, processes and products. As one consequence, the industry is far less likely to make drastic changes in materials — in both front-end transistor materials and back-end dielectrics — than it might have with a larger R&D time frame.

For instance, the industry is pushing oxynitride/poly gate stacks as far as possible before adopting high-k gate insulators and metal electrodes. Randhir Thakur, chief technical officer of the transistor and capacitor group at Applied Materials (Santa Clara, Calif.), explained, "Transistor scaling, especially gate length scaling, has been pulled in as much as six years for the 90 nm technology node. As a result, the transistor is approaching the physical limit in a much-accelerated fashion. For the 90 nm node, 37 nm gates with gate dielectrics consisting of only three to four atomic layers will be used in volume manufacturing. To deliver the manufacturing-worthy transistor gate stack with atomic-level dimensional control is a daunting challenge, and interface control will be vital."

If there is one aspect of the roadmap that has truly taken time to mature sufficiently, it is low-k dielectrics, evidenced by the incorporation of mostly FSG films at the 130 nm node. But there is a strong push to incorporate first-generation low-k materials (k~2.8) for the 90 nm node. "In the new roadmap, k values are much higher than they were in previous roadmaps. People are being a little more realistic about what one can achieve in the time frame available," explained Karen Maex, fellow at IMEC (Leuven, Belgium).

However, despite the limited introduction of some new materials, technology is progressing as fast as ever, taking manufacturing and design beyond the simple rules of scaling, which, combined with productivity enhancements, have allowed the industry to maintain Moore's Law all these years. For instance, silicon-on-insulator substrates are gaining wider use for high-performance microprocessors at the 90 and 65 nm nodes. Interplay between on-chip interconnect and packaging technology is coming to fruition, largely due to reliability issues associated with packaging chips with multiple layers of copper and low-k dielectric.

	Single-wafer ion implantation systems are addressing the need for more precise dopant placement for tighter well/well spacing as well as controlled S/D, HALO and pocket implants. (Source: Varian Semiconductor Equipment Associates)

Following the single largest year of revenue decline in semiconductor history, companies reacted by drastically cutting capital spending but actually speeding new technology development faster than ever before to remain competitive. In fact, it is largely in reaction to the overbuilding of fab capacity and subsequent downturn that device manufacturers and equipment and materials suppliers alike have had to follow an even faster roadmap beyond 180 nm devices and quickly into the 130 nm generation. The 1999 roadmap originally projected that the 90 nm generation (100 nm at the time), characterized by targets of 90 nm half-pitch on DRAM devices and a microprocessor gate length of 37 nm, would reach first production in 2005. Since the 1999 ITRS was drafted, these targets have been bumped to first production in 2003. Table 1 summarizes the 2001 roadmap targets.

For production manufacturing, 248 nm lithography with enhancements appears to hit a wall at ~120 nm. It is for this reason that 90 nm devices will primarily be patterned using 193 nm (ArF) lithography, with non-critical levels still using 248 nm. Though many researchers are pushing to ready 157 nm lithography for the 90 nm generation, it now appears that 157 nm will enter production instead at the 65 nm generation, which features a microprocessor final gate length of 25 nm and 65 nm contacts.

There are many significant challenges for 193 nm patterning, including CD control, overlay accuracy and transfer of the learning from 248 nm resolution enhancement technologies (RETs) to the 193 nm systems. Harry Levinson, manager of strategic lithography technology and fellow at Advanced Micro Devices (AMD, Sunnyvale, Calif.), said that "193 nm technology was delayed primarily because of the resists, but now those products are maturing and should be ready in time for the 90 nm node." He noted an interesting development, where some of the work on 157 nm resists is now being applied back to 193 nm resists.

"If you start looking at 193 nm photoresists from an etch perspective, the term 'resist' probably shouldn't even be in the name because it is much less etch-resistant than previous generations. This factor is causing many companies to use more hard masks, and even bilayer resist approaches," said Dave Hemker, vice president of new product development at Lam Research Corp. (Fremont, Calif.).

The 90 nm device generation calls for a 53 nm gate length in the resist, etched to a final length of 37 nm. Gate CD control in resist is only 3 nm (3s) (Table 2). "Gate CD control is really starting to get tough for microprocessors," Levinson said. "CD control on the masks, if we stay with 4×, which it looks like we will, may also become an issue."

"The lack of 193 nm resist robustness has required the development of new process regimes that deliver resist selectivities rivaling those of the 248 nm generation," said Kevin Fairbairn, vice president and general manager of conductor etch at Applied Materials. He said the etch process must also be adjusted to compensate for incoming lithography variations. "Integrated metrology helps address the challenge of tight CD control for logic gates by determining incoming resist CD variation and using feed-forward process control to modify the etch process and reduce the variation by a factor of 3."

Beyond the gate level, pattern control on contact masks is proving very difficult, due to the mask error enhancement factor (MEEF). "With some focused work, however, I think these issues will be resolved," Levinson added.

The extent to which RETs, including off-axis illumination, optical proximity correction and phase-shift masks, can be applied depends on the layer being imaged, the device type and the volume of product. However, Levinson notes that phase-shift mask technology has made a great deal of progress, and these techniques will be readily applied to 193 nm.

All in all, Levinson sees no showstoppers for the 90 nm generation. "This may be the last technology node that offers a clear path. We know of the improvements needed in masks, the 193 nm tools and the resists, but everything is starting to fall into place and we are getting comfortable with the technology. NGL is another story entirely."

The 45 nm technology node, slated for production in 2010, will likely require next-generation lithography systems, with the leading contenders being extreme UV lithography (EUVL), e-beam projection lithography (EPL), and 157 nm lithography.¹ Meeting this timeline will possibly require first-generation tools and masks by 2007. It may well turn out that certain methods prevail for an application, such as EPL's proficiency in patterning vias and contacts. Key to development of all of the techniques is meeting the technical goals in the given time frame, while providing acceptable cost of ownership and production capability.

The 90 nm generation is all about control: controlling CDs, overlay, defect levels on reticles and wafers, film thickness, dopant levels, dishing and erosion, stress between films, etc. All yield issues intensify with each technology generation. But the need to separate yield-killing defects from nuisance defects becomes especially important as you approach 90 nm.

The industry made serious progress in this area with the introduction of e-beam inspection systems that detect electrical defects using voltage-contrast technology. KLA-Tencor (San Jose) now takes that approach one step further. "Our in-line electrical defect monitoring solution provides non-contact electrical defect isolation, with customized test structures laid out such that they replicate the customers' design rules and bias," said KLA's Tom Long. The methodology allows accelerated yield learning by enabling the use of test structures at each conductive layer that represent the entire wafer surface within a very small area. The system's adaptive programming feature continually changes inspection criteria based on results. "Because we are isolating electrical defects in-line at each step, it is much easier than waiting for electrical probe and then going back and trying to isolate the defect using FIB/ SEM combinations. This reduces the learning cycle from many weeks to just a day or two."

Israel Beinglass, chief technical officer of Applied Materials' Factory Productivity Solutions (FPS) summarized the defect isolation, characterization and corrective action loop that results in faster yield learning in the fab. "Identifying the defect on the wafer is the first step, followed by patterned wafer inspection and automatic defect review and classification. Next, a defect source identifier application is used to provide root cause analysis. Corrective action then closes the loop of yield learning." He emphasized the importance of integrated diagnostic tools and advanced data mining.

The need for increasingly higher device drive currents (I_on) combines with the scaling of transistor gates to cause a requirement for better control of parasitic resistance associated with CMOS source and drain (S/D) regions. In the S/D, the process calls for abrupt junctions, both laterally and vertically, and high activation of dopant in the extension regions. The result? A requirement for low-energy, high-current ion implantation, but also tilt-angle capability (to 45°) to enable accurate, three-dimensional dopant placement (Fig. 1). New single-wafer, high-tilt-angle systems are addressing the need for precise placement of HALO and pocket implants in flash memory and logic devices.

 
1. Scaling trends drive the need for more precise dopant placement in the transistor using high-energy (wells), low-energy, high-current (S/D junctions) and medium-current systems. (Source: Varian Semiconductor Equipment Associates)

As with past technology nodes, rapid thermal annealing of the S/D junctions is required, preferably with instantaneous time-at-temperature (spike anneal) with tight, closed-loop temperature control.

Transistor engineering involves a comprehensive approach to well design, gate stack, ultrashallow junctions, sidewall spacers and low-resistivity contacts. The 90 nm node calls for a gate dielectric with an equivalent oxide thickness (EOT) of 0.9-1.4 nm, scaled down from 1.3-1.6 nm for 130 nm devices. Though the transistor was originally expected to include high-k gate dielectrics such as HfO₂, ZrO₂ or others, it now appears that nitrided oxides will be extended to meet the needs of the 90 nm generation, and possibly the 65 nm node. Single-wafer implanters are becoming necessary as the industry continues to scale device dimensions. A single-wafer approach avoids the cone angle effect, which is the variability of incident angle of the ion beam to the wafer surface with batch ion implanters. "The variability in implant angle is ±0.1° in a single-wafer system, where it's closer to ±1.5° in a batch tool," said John O'Connor, director of marketing for Varian Semiconductor Equipment Associates (Gloucester, Mass.). "A single-wafer system also provides more uniform parametrics across the wafer."

The 90 nm node will also feature greater use of double and triple wells for device optimization. For well formation, single-wafer, high-energy (0.5-2.0 MeV) implanters allow tighter well-to-well spacing, which is especially important for memory devices.

A new application for ion implantation is through-the-gate and through-the-spacer implants, which also require high-tilt-angle capability. "These applications potentially allow the user to reduce the total number of mask steps," O'Connor said.

But it is the high-current implant of shallow junctions that tends to steal the show in terms of doping performance. As junctions get shallower, the need for a high-current, low-energy implanter has produced new tools that use, for instance, pulsed plasma doping. These are expected to gain use at the 65 nm node. High-tilt-angle capability can also be used to preamorphize the S/D extension junction to limit the transient enhanced diffusion of the dopant species. With extremely short channels, the industry may use single-wafer systems to control the overlap between the S/D extension and the gate. "This capacitance has to be very small and, more importantly, very symmetric on each side of the gate," O'Connor said.

John Poate of Axcelis (Beverly, Mass.) enumerates the priorities at implant as including energy control, angular control, and mass and species control. "The battleground for ion implant is really the ultralow-energy, high-current implants for shallow junctions." Axcelis uses an electron confinement technology to deliver higher beam currents at 500 eV and lower. Poate added that the RTP step for S/D activation really depends on the issue of process control.

Win Shaw, also of Axcelis, emphasized a greater need for chained implants. "Including different types of devices in the same chip has made chaining more important, not only for productivity reasons but also yield."

Perhaps one of the most surprising changes at the 90 nm node is the decision to not change to high-k dielectrics. The high-k materials can achieve a thinner EOT with a greater physical thickness. According to the roadmap, the strongest driver for high-k gate dielectrics comes from the need to extend battery life for wireless devices due to lower leakage currents — including gate leakage, sub-threshold leakage and junction leakage. Therefore, the driver for high-k is low-power logic, not high-performance logic.

By switching from pure oxide to nitrided oxide dielectrics, the industry gets increased permittivity (allowing a physically thicker film to perform electrically like a thinner oxide), and some reduction in leakage currents. The nitride also acts as a barrier to boron, which can diffuse from the PMOS gate electrode into the silicon channel and shift threshold voltage.

Applied Materials, TEL and Mattson (formerly Steag) offer nitridation/oxidation processes for ultrathin gate dielectrics. In Applied's approach, the oxidation is performed in an RTP chamber using in situ steam generation, followed by plasma nitridation. "The oxidation step is really the key enabler, because the oxidation mechanism favors the best structure, oxide quality, which is less prone to leakage and, most importantly, it can be repeatably grown," Thakur said. He explained that the nitridation process, which uses a quasi-remote plasma source, controlled wafer temperature and a mTorr pressure regime, allows production of 1.2-1.4 nm film with 20× the leakage reduction relative to SiO₂ and <5% mobility degradation. Adding to the gate stack capability, Applied also offers selective oxidation processes for spacer formation along with ultrashallow junction implant and spike anneal. Because the company offers nearly all equipment to manufacture the entire transistor, Applied is extending its portfolio beyond the films, equipment, process capability and structural analysis to providing electrical data using short loops.

Tokyo Electron Ltd. (TEL, Austin, Texas) offers three approaches to forming nitrided oxide dielectrics. The first, which has been in production the longest, involves a standard furnace oxidation that incorporates nitrogen thermally in the latter stages of growth by adding NO or N₂O. The second approach conserves thermal budget, while allowing better physical and electrical characteristics. It uses a plasma SPA (slot plane antenna) source to introduce nitrogen into a pre-grown oxide. Finally, TEL offers an oxidation/CVD process where the thermal oxide is grown and CVD nitride then deposited in a fast-ramp furnace.

Bob Soave, TEL's strategic technologist, believes customers will use one of the two latter approaches in the manufacture of sub-100 nm devices. "People are evaluating the zirconium and hafnium oxides for high-k, as well as their silicates. In theory, the silicates can give you better thermal stability, but this comes at the expense of lowering the k value. However, it still hasn't been clearly proven that the addition of silicon to a HfO₂ or ZrO₂ will actually improve the film's thermal stability."

As with the copper and low-k dielectric transition, companies are trying to determine whether it makes sense to incorporate a new high-k dielectric with polysilicon first, or to first change the metal electrode. Soave sees the comparison stopping there. "The advanced gate stack will make copper and low-k look like a walk in the park."

Industry consensus is leaning toward incorporating the high-k dielectric first. HfO₂ and ZrO₂ are leading candidates, both due to their compatability with standard self-aligned gate processes and good interfaces with poly and TaN gates. Nitrogen can also be incorporated into these films to suppress boron diffusion.² However, too much nitrogen can negatively influence stress hysterisis and increase interface trap density.

For optimal performance and reliability, IC companies are likely to use a dielectric stack, perhaps of up to three different materials. Chris Werkhoven, vice president of central strategic marketing at ASM America (Phoenix) explained that atomic-layer deposition is well suited to depositing thin dielectric layers that could combine Al₂O₃, HfO₂ and NO, for instance. "The need to optimize both the interface with the gate and the interface of the silicon will lead to such high-k stacks," he said.

Contact technology is also evolving with the scaling of transistors. CoSi₂ contacts have replaced TiSi₂ films at the 90 and 65 nm nodes. But a further material change to nickel or Ni/Co combinations may be needed as soon as the 45 nm generation to lower resistivity at the same thickness. "Since you want the scaling in both the vertical and lateral directions, people are looking at nickel silicides, certainly beyond 70 nm," said Ludo Deferm, vice president of business development at IMEC. "But there are still a lot of things which have to be investigated, such as stress, compatibility with the junctions, and a lot of material aspects have to be investigated."

Though many advanced logic companies are moving copper into production at the 130 nm node, several challenges remain, especially related to barrier and seed layer scaling and copper CMP. Post-CMP defects remain a crucial problem. "Managing post-CMP defects, amazingly enough, is very related to the barrier/ seed process," said Victoria Shannon, vice president of integration and applications for Novellus Systems (San Jose).

"Probably the biggest yield issue is copper voiding — voids in the vias," said KLA-Tencor's Long. "In addition, we see quite a few problems of residual copper after CMP. These high spots end up causing shorting between copper lines."

With the softer low-k dielectrics, companies are evaluating low downforce processes (0.5-1.5 psi) and abrasive-free slurry approaches as well. "Closed-loop process control is proving essential to uniform, production-worthy CMP," said Paul Cheng of Lam Research. He added that integrated optical metrology, which can monitor metal residue or oxide erosion, is also becoming more important.

The spin-on vs. CVD low-k battle seems to have been finally decided, with the industry choosing both options. Both the low-k polymer from Dow Chemical (Midland, Mich.) and the various organosilicate glass (OSG) CVD films, also referred to as carbon-doped oxides, are entering production at the 130 nm node. Integration has always been the issue defining the choice of low-k dielectric, which is why many IC companies have yet to choose a low-k film (k~2.8) for their devices.

If there has been a showstopper that has kept low-k dielectrics from adoption, it is packaging. "We perform all of our reliability testing of copper and low-k materials using packaged devices," said Shannon. Maex added, "The first issue is, can we package low-k dielectrics in a safe way, and that's definitely something we have to evaluate for the porous dielectrics. Then, once we know the good way to do that, can we provide extra functions within the wafer-level package." She continued, "We are looking at one or two distribution layers on the chip, as well as putting coils into them for inductors, or incorporating transmission lines. This gives us an additional degree of freedom."

Much integration work goes into optimizing adhesion of films and balancing stresses to give mechanical and thermal stability in the stack. "We've taken it beyond wafer-level integration to include wire bonding, C4, flip-chip technology, the type of molding compounds, and stress-induced issues," said Farhad Moghadam, vice president and general manager of the Dielectrics Systems and Modules Group at Applied Materials. Through partnerships with packaging houses and customers, companies like Applied are proving the packaging reliability of devices that use their low-k films. According to Moghadam, even the choice of soldering materials has become important since the composition of the solder can impact the amount of stress on the substrate.

Customers are strictly weighing which low-k material is absolutely needed on a layer-by-layer basis. "We can balance stress between our low-k film and barrier, which becomes especially important when you go to eight levels of metal," Moghadam said. Of course, as the low-k, barrier and etch stop films scale from the 130 to 90 nm generation, process control becomes more essential. "We are using integrated closed-loop and feed-forward process control between our copper/low-k interconnect systems to enhance productivity and performance. For instance, communication between our deposition and etch equipment improves etch depth control, which widens the etch process window and improves via and line resistance distributions." The company also uses modeling to feed information from the ECP system to CMP to improve metal resistance.

The 90 nm technology node calls for dielectric with an effective k of 2.6-3.1, which would imply an intermetal dielectric with k value in the 2.2-2.4 regime. However, first-generation incorporation of low-k dielectrics mainly in the ~2.8 regime is likely to yield integrated k_eff >3.1 in some cases. IC companies are also weighing how aggressively they should pursue lower k values, since films with moderate k value usually prove easier to integrate. Whereas device manufacturers were requesting k=2.0 for second-generation low-k, it now appears that k=2.4 may be sufficient. Then, companies can scale down k_eff by thinning barrier and hard masks, incorporating low-k hard masks such as SiC-based CVD films, and even eliminating interlevel etch stops between the trench and via in a via-first dual-damascene scheme. Such approaches will extend the life of the low-k material once it is put in production.

Low-k dielectrics precede copper by two years for DRAM manufacturers, who largely will adopt first-generation low-k materials (k~2.8) at the 130 or 90 nm nodes. Keith Buchanan, process integration manager at Trikon Technologies (Newport, UK), explained that, in going from the 130 to 90 nm generations, the ILD gets scaled down due to the aggressive scaling of metal pitches and metal aspect ratios. "The consequence is that the dielectric between the lines is thinner and you must also thin the hard mask and etch stop, which makes the etch process more difficult, or you can reduce the k value of the hard mask and/or etch stop," he said.

Maex summarized some of the key challenges in low-k integration. "There is the cleaning after patterning, dimensional control, which is very important, the integrity of the metal barrier and the mechanical stability during copper metalization, as well as mechanical and thermal stability during packaging." Figure 2 summarizes what can go wrong with copper/low-k combinations.

 
2. Scaled multilevel metal interconnects are susceptible to a number of integration issues involving the low-k interlevel dielectric, barrier/seed interface and copper fill and CMP. (Source: Applied Materials)

Among the many candidates for low-k films are offerings of CVD films by Applied Materials, ASM International, Novellus Systems and Trikon Technologies. Most of these companies have scaled their low-k films to 2.4; others claim 2.0 and below. Key to film comparison is the percentage of air present in the material at a given k value, hardness, modulus, stress, etc. However, the industry has really moved beyond comparing physical characteristics of the film to comparing dual-damascene integrated device results and fully packaged chip reliability.

The leading spin-on candidate is Dow Chemical's SiLK film, though MSQ and porous silica products from Dow Corning (Midland, Mich.), Honeywell (Sunnyvale, Calif.), JSR (Tokyo) and Shipley (Marlborough, Mass.) are gaining exposure. Dow Chemical recently introduced a low-k etch stop material, though the film has also shown compatibility with SiC-based CVD etch stops and hard masks.

"You get much more out of your dielectric if you have low-k hard masks, etch stops and dielectric barriers. Changes such as these will allow us to push one technology node further without having to go to porous materials," Maex said. She added that, in some cases, the hard mask is the same material used for patterning. "That is a big advantage because it's a one-material system that is fully optimized."

Cleaning processes are still being optimized for low-k and will undoubtedly undergo further changes when next-generation porous low-k films (k<2.4) are incorporated. "The cleaning processes right now are wet and we'd like for them not to be," said Ralph Butler, low-k integration marketing manager for TEL. "We need to fully understand how pores are etched and how a porous structure interacts with wet chemistries."

Process sequence is also important. "We explored wet clean before barrier open and after, and we saw significant differences in the reliability of the copper film," Shannon said. "Adhesion between the dielectric diffusion barrier and the copper line, especially in the area of the via, is important. These are key areas with respect to electromigration performance and stress migration performance."

A significant hurdle for CVD films has been optimizing etching, stripping and cleaning processes so they would not strip carbon out of low-k films, thereby raising k_eff. IC manufacturers would also like options with respect to cleaning processes. "We deliver two processes — one two-step dry process which removes the photoresist and then etches the post-etch polymer, or we have a dry/wet combination that uses an EKC remover after plasma treatment," explained Trikon's Buchanan.

A key challenge for the softer, porous dielectrics will be integration with the metal barrier. "Liner technology is probably the biggest roadblock to adopting porous low-k because the material can be etched, but you need to remove the residue on the sidewalls and the liner must then fully cover the pores," explained Lam's Hemker. The roadmap shows barrier metals scaling to 5 nm and thinner, which will be challenged to passivate the region between porous dielectric and copper.