Optical Lithography as the Pink Bunny

Certainly, the industry knows that optical lithography has its limits and — someday — those limits will actually play out. But optical techniques continue to buck predictions, their capabilities moving past the 1 µm mark, then past 0.5 µm ... then past 0.01 µm? In fact, a group at MIT's Lincoln Laboratory (Lexington, Mass.) has reported the optical fabrication of a 9 nm gate. It seems that optical lithography just keeps going...

The group had previously fabricated 25 nm gate length fully depleted SOI transistors, using 248 nm (KrF) lithography with double-exposure chromeless phase-shift masks (PSMs). The latest work is an extension of that, using a tuned etch bias to fabricate a 9 nm gate length SOI transistor.

This process was achieved in a laboratory, and has not been proven in a manufacturing environment. Also, the finished device was not electrically functional because the appropriate channel engineering had not been performed. However, despite these factors, the achievement indicates the incredible potential that optical lithography still has. And, while the industry may not realistically be looking to produce 9 nm gates with a 248 nm lightsource, this does point to the feasibility of KrF lithography for the 100 nm node.

Strong phase-shift or alternating aperture phase-shift methods permit lithography processes with k₁ factors as low as 0.3 for dense features. Isolated resist gate features as small as 40 nm are possible using double-exposure PSMs with a 0.6-NA KrF tool. By realizing a lithography process with k₁=0.3, a state-of-the-art 0.75-NA KrF tool should be able to resolve dense 100 nm l/s features. With the mature infrastructure of KrF technology (especially resists), some chipmakers may find KrF lithography well-suited to 100 nm node features. Extrapolating their results with KrF lithography, the researchers at Lincoln Laboratory suggested that their methods could be used to produce chips at the 70 nm node with 193 nm (ArF) lithography, and at the 50 nm node with 157 nm (F₂) lithography.

To address proximity control issues in strong phase-shift lithography, the group has developed a PSM method called GRATEFUL (gratings of regular arrays and trim exposures for ULSI lithography). The method eliminates proximity effects, thereby eliminating the need for optical proximity correction (OPC). In addition, the PSM "masters" can be re-used for different circuit designs and levels, lowering PSM costs, speeding turnaround time, and simplifying mask inspection.

To read more about this work and its implications, see "Optical Lithography: No End in Sight?" by Tracy Weed, Numerical Technologies Inc.

For additional information on lithography, go to www.semiconductor.net/lithography