2001 Roadmap Identifies R&D Targets, Showstoppers

As the semiconductor industry leaves behind 2001 — its greatest year of market decline ever — it demonstrates how now, more than ever, technology acceleration is essential to the future prosperity of electronics and semiconductors. The 2001 version of the International Technology Roadmap for Semiconductors (ITRS) includes several changes: the acceleration of scaling, particularly of microprocessor gate lengths; the deceleration of low-k dielectric adoption; the accelerated need for high-k gate dielectrics; and the addition of an emerging technologies section that describes alternatives to standard CMOS.

The new roadmap also contains what appears to be a shift in device generation — to 90, 65, 45, 32 and 22 nm, from 100, 70, 50, 35 and 25 nm in previous editions. However, "all we're doing is analyzing and expanding the scaling using the factor 0.7× for every generation," explained Paolo Gargini, Intel fellow and ITRS committee chairman, at the recent ITRS press conference. "The old names were established over 10 years ago, and at that time they were close enough to identify specific technologies. But as we get closer to implementation, we need to be more accurate."

Despite two-year technology node cycles from 1995 through 2001, the ITRS committee, comprised of more than 800 participants worldwide, expects the 90 nm technology node as well as future nodes to be separated by three years. The device technology node is defined as the scaling of half-pitch for DRAM devices (180 nm pitch for 90 nm devices), which is expected to continue on a three-year cycle. MPU gate scaling, however, will continue to follow two-year cycles until the 32 nm node (2005). MPU half-pitch stays on a two-year cycle until 2004 at 90 nm, and is then expected to follow a three-year cycle. As the roadmap states, identification of the 90 nm technology node in 2004 does not preclude an introduction by some companies of a 100 nm device generation in 2003, for instance. A node is reached when two companies produce 10,000 units/month in a year.

While there is agreement on these technology targets, it is still altogether possible that the industry could continue its two-year cycles, even with the tremendous technological and economic considerations associated with producing new transistor gates and 10-level copper interconnects with low-k dielectrics in high-performance packages.

Industry progress and the imminent challenges can be gleaned by comparing the 1999 and 2001 roadmaps (Tables). However, despite progress in forming ultrashallow junctions and thinner, high-reliability barriers to copper, the industry is now two years closer to the "red brick wall." The wall could be reached as early as 2003, but more likely closer to 2005.

(Source: 2001 ITRS)

Red parameters in the roadmap signify one of two things: that there is consensus that a particular value will ultimately be achieved (perhaps late), but for which little confidence exists in currently proposed solutions; or where consensus exists that the value will never be achieved (progress will end or some work-around will render it irrelevant).

The near-term grand challenges (³65 nm) are primarily focused on design and test, lithography, front-end processing and process integration. CD control, particularly of gate length, has become especially difficult. Because the fine etched feature is considerably smaller than that patterned in photoresist, more complex etch processes must be executed while maintaining <15% 3s dimensional tolerance. Shrinking MPU gates and increased mask error factors associated with low-k₁ lithography is making mask CD control more difficult. Control of self-aligned doping processes and thermal activation budgets must allow a <25% 3s change in L_eff. Better metrology methods are needed to measure doping profiles in two dimensions and defects at the bottom of trenches and vias.

In the area of performance enhancement, the move to high-k gate dielectrics will be driven by the needs of low-power logic where extended battery life is desirable. The cost-effectiveness, process control and reliability of ultrathin oxynitride gate dielectrics will be key as gate leakage continues to increase. Metal electrode gates are expected by 2007, which must be compatible with high-k dielectrics, and hopefully with standard CMOS device structures (i.e. avoiding replacement gate approaches).

At the 65 nm node, new device structures such as double-gate transistors and ultrathin body SOI devices will begin to emerge. These structures will eventually be necessary to control short-channel and other effects in drastically scaled devices.