Isolating Defects: The Ones You See and the Ones You Don't

Defect inspection and review was difficult enough when you could see killer defects, even if it was only with a SEM. Now, with the 2001 update of the International Technology Roadmap for Semiconductors (ITRS), attention is being called to the exponential increase in fault isolation complexity, needed in both the vertical and horizontal planes. Some circuit failures actually leave no detectable physical remnant — like a poly stringer or metal void. The industry needs methods for testing and diagnosing these electrical failures.

The roadmap also highlights significant yield issues with respect to copper interconnect and dual-damascene structures (Table). The industry needs a method for detecting voids in copper lines. There also is a need to measure the CDs of very high-aspect-ratio structures, hopefully providing CD information about trenches, vias, contacts and their sidewall profiles. Most insidious are defects near or at the bottom of damascene trenches, highlighted as a grand challenge in the roadmap. With the scaling to 90 nm dimensions comes a need to identify any defect ~40 nm in size. Without the combination of high throughput and high sensitivity, these measurements cannot be made in-line.

 
 (Source: 2001 ITRS)

With the imminent introduction of new materials, the industry is also in need of reference materials and standard measurement methodologies for high-k gate dielectrics and capacitor dielectrics with their interface layers. Other thin films such as metal interconnect barriers and low-k dielectric barriers will need similar capability. Stepping back, the industry needs to understand how electrical test structures might have to change to reflect the properties of new materials such as high-k dielectrics and metal electrodes. Models are needed that can consider such things as dielectric constant, surface states, reliability, breakdown and tunneling as they relate to process and material conditions.

Test structures are undergoing evolutionary changes too, despite the shrinking dimensions of scribe lines. For instance, overlay is sensitive to process variation, and test structure must be improved to ensure correlation between scribe line measurements and on-chip properties. To develop stable reference materials, the standards organizations need access to state-of-the-art development and manufacturing capability.

The 2001 roadmap also emphasizes a need to integrate yield management systems in the fab with WIP management systems. Standard, easy-to-integrate interfaces are required for advanced process control and equipment control. The roadmap also added a new section on wafer environment control. Further, there is a growing need to monitor particles on the wafer backside.

From a practical standpoint, there are serious return-on-investment issues associated with all metrology and yield management tools. Because their capability should be available about two years ahead of other process tools (PVD, CVD, etch, etc.), the metrology tools will not be purchased in volume until perhaps two years after introduction. The industry is not certain how to address this issue.

For additional information on yield management, go to www.semiconductor.net/yield