New Transistor Designs Offer Improved Performance

Among the many new technical breakthroughs announced at last month's International Electron Devices Meeting (IEDM) in Washington, of special interest are new transistor designs developed by companies such as Intel, IBM and Agere. These new designs, which include raised source/drains, double gates and vertical transistors, could result in dramatic improvements in transistor speed, power efficiency and heat reduction.

Intel described results of a "thin-silicon-body depleted substrate transistor" and presented high-frequency results of transistors fabricated with high-k gate dielectrics. Intel said that together, these advancements dramatically reduce current leakage and power consumption (although, curiously, it did not report any results where the technologies were actually brought together).

Not to be outdone, IBM Microelectronics announced a "double-gate" transistor that it says can carry twice the electrical current, operate at up to twice the speed and be reduced in size well below today's conventional transistors. And Agere Systems, in work with Bell Labs and ASM America, reported on a vertical replacement gate device with a high-k gate dielectric.

The structure under development by Intel (Santa Clara, Calif.) is being called the TeraHertz transistor. The company is expected to begin incorporating elements of this new structure into its product line as early as 2005. One element is a depleted substrate transistor, where the transistor is built in an ultrathin layer of silicon on top of an embedded layer of insulation. This ultrathin silicon layer, which is different than conventional silicon-on-insulator (SOI) devices, is fully depleted to create maximum drive current when the transistor is turned on, enabling the transistor to switch on and off faster. Also, when the transistor is turned off, unwanted current leakage is reduced to a minimum level by the thin insulating layer. This allows the depleted substrate transistor to have 100× less leakage than traditional SOI schemes.

	1. Intel’s TeraHertz transistor (right) has three new features: a new gate dielectric, a layer of oxide buried within the silicon, and raised source and drain. (Source: Intel)

Intel researchers also reported the first measurements of the high-frequency response of transistors fabricated with high-k gate dielectrics. Although work on these high-k materials, such as ZrO₂, HfO₂ and Al₂O₃, has been underway for some time, only dc and low-frequency parameters have been measured. The good news was that there were no surprises when it comes to high frequencies — the devices showed results similar to those of CMOS transistors with SiO₂ gate dielectric for similar physical gate lengths. This lead the researchers to conclude that high-k gate dielectrics "are suitable for high-performance microprocessor applications."

In the double-gate structure being developed by IBM (White Plains, N.Y.), the channel is surrounded by two gates, doubling control of the current and enabling significantly smaller, faster and lower-power circuits. IBM overcame a number of challenges that have held back the research of these experimental double-gate transistors at labs throughout the industry, taking a significant step toward manufacturability. Improved transistors such as the double gate are expected to be needed in five to 10 years, when transistors shrink so small that it becomes difficult to shut them off. For example, in one version a planar, triple-self-aligned, double-gate structure was fabricated using chemical mechanical polishing (CMP) at multiple stages during front-end processing.

The research team from Agere Systems (Allentown, Pa.), Lucent Technologies' Bell Labs (Murray Hill, N.J.) and ASM America (Phoenix) also made significant progress in the high-k gate dielectric area, demonstrating the shortest-gate-length high-k transistors ever reported; the first HfO₂ dielectric deposited by ALD; and the first vertical transistors with high-k dielectrics. The vertical replacement gate structure, introduced in 1999, comprises vertical MOSFETs built on the walls of a silicon channel. Advantages include a higher drive current per unit area of Si, the stacking of transistors and storage capacitors, and control of the gate or channel length without lithography (it's instead controlled by deposited film thickness). In the most recent work, the polycrystalline HfO₂ films exhibited extremely low gate leakage current.

For additional information on wafer processing, go to www.semiconductor.net/wafer