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Movin' On Up

Peter Singer, Editor-in-Chief -- Semiconductor International, 1/1/2002

Matrix Semiconductor (Santa Clara, Calif.), a fabless company, may have come up with a dream scenario for a foundry. Using the conventional tools and technologies in place at TSMC, Matrix plans to build a radical new type of memory device that is built upward into the 3-D plane to achieve an ultradense chip. Matrix says that, by building upward, it can achieve a tenfold cost reduction compared with existing technologies. "The fact that this is a stable, single high-volume product makes them very interested, especially since they don't have to do anything new in the fab, such as introduce a new material," said COO Siva Sivaram.

The first product based on the new technology will be the Matrix 3-D Memory, the first semiconductor memory developed for use as a "consumable," much like traditional camera film or audio tape. The initial markets for this first product will include archival storage for portable electronic devices such as digital cameras, digital audio players, portable games, PDAs, cell phones and others. The technology could also be used as a medium for pre-recorded content such as music, electronic books, games, digital maps and reference guides.

Memory cards based on Matrix 3-D Memory will be write-once, available in standard flash card form factors, and interchangeable with standard flash cards. Presently, Matrix has a 64 MB (512 Mb) write-once memory in production, "meaning the masks have been taped out and wafers are in-line," Sivaram said. He added that "8 Mb parts have been through the fab, assembled, and are being tested here and going through reliability studies," and that the plan is to optimize the 64 MB device. "Our first product is the 64 MB write-once memory. Our immediate job is to get that as optimized as we can, then move it down the standard technology curve, from 0.25 µm down. Densities will be driven by the market, but we want to commercialize the 3-D technology in all its forms."

 
1. The Matrix 3-D chip consumes less wafer area, as well as less vertical area compared with a standard IC microprocessor. (Source: Matrix Semiconductor Inc.)

Matrix and its technical team have been granted two U.S. patents covering the inventions around 3-D semiconductor design and production, and have filed more than 60 additional applications.

"Matrix Semiconductor has proven that building 3-D semiconductors is not only possible, but that it can be done in a practical and cost-efficient way that is consistent with high-volume requirements," said Steve Cullen, director and principal analyst, Cahners In-Stat Group's Semiconductor Research Services. "This breakthrough provides new promise to an industry challenged with sustaining the fast-paced growth the market has come to expect. By building semiconductors in three dimensions, Matrix Semiconductor demonstrates an achievable, elegant and scalable way to introduce ultradense, low-cost chips. The market opportunities are enormous."

 
2. This SEM cross section is the first truly 3-D IC, according to Matrix. The memory layers are shown. (Source: Matrix Semiconductor Inc.)

Figure 1 shows how the Matrix 3-D chip differs from a standard IC. Where the layers above the substrate in a standard chip contain only insulation and interconnect (wiring), the 3-D chip contains layers of active devices (but no transistors). In this example, the Matrix chip contains eight memory layers. "The basic technology consists of two levels of interconnect in a normal CMOS process at the substrate. The memory layers are built on top of the substrate," Sivaram explained. "Multiple memory layers are made with this diode and antifuse combo above the substrate, and those are fabricated in polysilicon. Ultimately, there is one layer of metal on top that provides power and ground." Figure 2 is a SEM photo of the memory layers.

The technology to achieve this was only recently developed, thanks to the polysilicon deposition and in situ doping work done to develop thin-film transistors for flat-panel displays, Sivaram added. CMP also plays a key role. "If I want to make eight layers, I have to have pretty good planarity going up," he said.

For additional information on emerging technologies, go to www.semiconductor.net/emerging

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