'Chips-First' Technology: Has Its Time Finally Come?

Intel (Santa Clara, Calif.) recently announced its bumpless build-up layer (BBUL) packaging technology, for use by its most powerful processors beyond the year 2007. This is really an implementation of an almost 20-year-old technology — "chips-first" packaging.

In conventional packaging, a substrate is fabricated and tested. Independently, a chip is fabricated and tested. The chip is assembled onto the substrate either by wire bond or flip chip. In chips-first packaging, the chip or chips are mounted face up to an inert substrate and the interconnect is built sequentially on top of the chip, using any number of HDI approaches. The chip is the first step in building the package.

This approach was pioneered and widely used by General Electric in the 1980s as an early MCM technology. A number of satellites flying today have MCMs with chips-first packages. The technology was later transferred to Texas Instruments in a program funded by the Defense Advanced Research Projects Agency (DARPA) in hopes of taking advantage of commercial opportunities for the fledgling MCM industry.

	Cross section of BBUL substrate. (Source: Intel)

If this technology is so great, why isn't it in volume production today? It's the old "bang for the buck" tradeoff. The cost of chips has been extremely high measured in risk and dollars and, given the state of leading-edge chips until now, a comparable bang can be achieved using more conventional packaging approaches such as flip-chip attach and HDI substrates. Only space-based systems have demonstrated that the total cost savings from smaller size and weight justify the higher component cost, commercial and technical risk . . . perhaps until now.

Intel and the rest of the semiconductor industry have been riding Moore's Law since 1965, in that the number of transistors on the most cost-effective chip will double every 18 months. The Pentium 4 processor has more than 40 million transistors. Given the advances of lithography and fabrication technology, it's easy to extrapolate that, by about 2007, there will be 1 billion transistors on a chip.

Koushik Banerjee, technical advisor in the Assembly Technology Development Division of Intel, suggests four significant packaging challenges for the giga-transistor chip: the silicon-to-package interconnect, within-the-package interconnect, power management and the opportunity of adding functionality — all, of course, in high-volume production and at low cost.

Extrapolating to the giga-transistor chip, he anticipates more than 10,000 I/Os will be coming off the chip. As differential signaling proliferates, this number might even grow. Making the interconnects between these pads will require more than 40,000 microvias in the package. At these densities, the package substrate will look more and more like an extension of the chip interconnect.

It is scary anticipating the power demands of the giga-transistor chip. Even with reduced supply voltages, the power dissipation of current-generation Pentium family processors is more than 70 W. The two challenges are getting clean power into the chip and the heat out. Reducing the rail collapse from delta I noise will require higher on-package capacitance and lower chip-attach inductance. Every generation of integration level requires a doubling of the decoupling capacitance and halving of the associated loop inductance.

Though heat removal from the system is dominated by the box design, getting the heat from the chip to the heat sink interface is part of the packaging solution. Current processors ship with an integrated heat pipe. The thermal interface between the chip and heat pipe can dominate the overall thermal performance.

The future is as inevitable as Moore's Law. The packaging challenges of the giga-transistor chip will be hard to meet by extending the leading-edge conventional approaches. Maybe Banerjee is right — that chips-first technology has the potential to meet the chip I/O, interconnect density, power distribution and integration needs. Surely, with the volume requirements of Intel processors driving it, the commercial and technical risks will be dramatically reduced.

For additional information on assembly and packaging, go to www.semiconductor.net/assembly