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Integrated FET Devices Achieved With Carbon Nanotubes

Brian Dance, Contributing Editor -- Semiconductor International, 12/1/2001

A research group at Delft University of Technology (Delft, Netherlands) has fabricated logic gates using FETs that are based on carbon nanotubes. The successful integration of a number of these devices onto a single chip is said to represent a significant advance. Such integration was impossible with the structure used in the earlier nanoscale devices, most of which employ a back gate that applies the same potential to all of the transistors on the chip.

The researchers, led by physicist Cees Decker, have fabricated a circuit that has an aluminum gate under which there is an insulating layer of aluminum oxide just a few nanometers thick, and a semiconductor nanotube. This thin dielectric layer provides for good capacitive coupling between the gate and the nanotube.

Three main steps are used to fabricate these FET devices. The aluminum gates are first patterned onto the silicon wafer substrate by using e-beam lithography. The thin insulating aluminum oxide layer is grown by simply exposing the aluminum gate to the air. The nanotubes to be used are dispersed onto the wafer surface from a dichloroethane solution. An atomic force microscope is used to select those tubes with a diameter of ~1 nm. The nanotubes are not doped initially except for their very slight natural p-type doping. However, the nanotube channel can be doped by simply varying the gate potential to move the nanotube from the valence band first into the energy bandgap and then into the conduction band. The addition of electrons in this way can result in the bridging of the gap. This enables a full p- to n-doped range to be obtained.

The Delft group has already constructed circuits on the nanoscale that each contain an inverter, an SRAM cell and a ring oscillator. The researchers suggest that the fabrication of such nanoscale integrated circuits in this way offers a means for overcoming the physical limitations to the miniaturization of circuits through the use of conventional lithographic techniques.

For additional information on materials science, go to www.semiconductor.net/materials.

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