Optimizing Yields in Embedded Memory Devices

HPL Technologies (San Jose) recently joined fabless firm Virage Logic's (Fremont, Calif.) Memory Alliance Program (MAP) to enable the production of high-yielding embedded memory devices early in the design and pilot manufacturing phases. Virage Logic's STAR SRAM-based Memory System, introduced in July, integrates the test and repair of embedded memories onto system-on-a-chip (SoC) devices. HPL offers flexible software platforms designed to accelerate the process of identifying, measuring and correcting sources of failure in the IC production process. By combining the STAR system with HPL's yield enhancement tools and services, users can obtain higher manufacturing yields through failure analysis and optimization of embedded memories.

The integration will occur in two phases. First, HPL will project the SoC's manufacturing yield so that the fabless designer can optimize the selection and implementation of the redundant elements within each STAR memory. Then, the amount of redundancy in each memory can be adjusted and optimized. HPL's layout analysis and fault extraction software is next used to determine which memory defects are likely to occur, and the STAR system's built-in self-test (BIST) capability can be programmed to detect those faults.

In the second step of implementation, the companies will use actual production data along with results from manufacturing test to further increase the test and repair capability in the memory device to best balance yield, reliability, testability and cost.

Before this approach, the second step would normally occur during high-volume production. The earlier incorporation of BIST and yield analysis will help speed to market higher-yielding devices. These yield enhancement tools are available to Virage Logic's customers.

For additional information on yield management, go to www.semiconductor.net/yield.