Yield Learning Cycles Blast Off at Warp Speed

The length of yield learning cycles (the ability to find, characterize and correct the defects that limit yield on new processes), which can last up to eight weeks and cost millions per day, has been an endemic problem in semiconductor manufacturing, particularly with shrinking market windows. Simultaneously, the industry is struggling to cope with the increased expense and manufacturing roadblocks involved in bringing technologies like copper, sub-wavelength lithography and 300 mm wafers into production (Figure).

Addressing the need for accelerated yield learning, KLA-Tencor (San Jose) has introduced µLoop ("MicroLoop"), the first non-contact in-line electrical defect monitoring system for volume IC production. By bringing electrical test into front-end wafer processing, the system can potentially reduce yield learning cycles' length from weeks to a few days, with the concomitant advantages and savings. The company expects it to do for yield acceleration today what in-line optical defect monitoring once did to revolutionize yield learning, with its capability to detect yield excursions in real time instead of waiting weeks or months for product wafers to reach electrical test or wafer sort.

This potential improvement in speed and quality of yield learning could enable IC manufacturers to substantially accelerate the ramp-up of new designs to full-volume production, as well as increase baseline yield. This is extremely important when considering that a new fab can yield millions in added product revenue for each day saved in bringing it on-line, which can add up to hundreds of millions of dollars annually, depending on the setup.

 
As process complexity and steps trend upward, meeting the yield learning challenge becomes more important, as does the identification of difficult-to-isolate killer defects that must be identified faster and with greater certainty. (Source: KLA-Tencor)

Because each process may have several critical yield issues that need to be resolved, it can take as long as nine months for a new process to reach yield maturity. Clearly, having a reliable real-time defect detection capability in the fab that enables faster and higher yield can have a considerable impact on a company's bottom line.

µLoop uses a combination of existing and new process control technologies, including patented test structures that replicate customer-specific processes, design rules and products, allowing the user to reliably set the system to work on specific issues. Other components are the eS20XP e-beam inspection and eV300 e-beam review systems, which use a voltage-contrast technique to identify and characterize electrical defects. Results are then run through electrical defect and yield analysis software, which filters out non-yield-relevant defects to show only those that directly impact device performance.

The test structures used by the system are optimized to simulate the patterns of a given process layer. The user can then scan only a portion of the test structures to quickly determine the exact location of electrical defects on a wafer within minutes. Once the e-beam review system has classified the defects, the electrical defect locations can be overlaid with physical defect data obtained by optical inspection tools to determine the cause, step and location at which the electrical defect occurred. Fab engineers can then adjust their optical inspection tools to increase the capture of physical defects that correlate to electrical defects. This further refines the defect control process, at the same time reducing the need for off-line or end-of-line wafer probing and freeing up engineering resources to concentrate on fixing yield problems instead of identifying them.