Yield Learning on 300 mm Wafers

At the upcoming IEEE IEDM conference, Intel's Bob Gasser will reveal the process design, development and learning engine the company used to achieve rapid yield ramp of logic devices including the methods used to produce 0.13 µm devices on 300 mm wafers. The strategy that Intel (Santa Clara, Calif.) follows involves designing the process for high performance, which ensures that the development engine delivers new process technologies at continuously increasing yields and increasing volumes.

With each successive generation (from 0.25 to 0.18 to 0.13 µm) Intel was able to improve factory line yields faster (Fig. 1) through design-for-manufacturing techniques, which make extensive use of error analysis in setting process targets. Process window experiments and design structure validation were used to verify the targets. Finally, Intel used excursion protection and statistical process control (SPC) capability as a part of its shop flow control system to detect process drift and instability more rapidly.

Between generations, the process capability (C_pk), stability and excursion resistance, and the start of high-volume ramping also improved. By tying advanced process control (APC) techniques to process variations that directly affect the performance and reliability of the transistors — gate delay, for instance — the company is able to best optimize

	1. With each successive device generation, the fabs have been able to achieve faster driving of defect density over shorter periods of time. (Source: Intel)
	2. Line yield trends during the last quarter of development and first quarters of ramping for logic devices. (Source: Intel)

Since the 1980s, Intel has used its copy-exact methods for all fab technology transfers, beginning with the 0.5 µm generation of products. The method uses key process monitor or output matching as well as partial recipe or input matching in cases where the input parameters are expected to impact yield, device performance or reliability. The company's 0.13 µm technology is currently being ramped and has demonstrated the highest initial yield levels to date, even given a full copper interconnect structure.