5× Reduction Possible with Selective SiGe Etch

In yet another indication that conventional technology will be extendable for years to come, French researchers at STMicroelectronics (Geneva) and France Telecom R&D

The new research will be presented at the International Electron Devices Meeting next month (see "IEDM Highlights" below). According to an article pre-print provided by conference organizers, the researchers report that the main issue in nanometer MOS devices is to pattern the gate in a controllable manner. Since the resolution of standard lithography (and even e-beam) is limited, the team used a gate stack made of 500 Å of amorphous SiGe, 1000 Å of polysilicon and a 2.75 nm gate oxide (Fig. 1). Using selective etching of the SiGe alloy, the researchers were able to take a gate with a starting dimension of 80 nm and thin down the bottom of it to only 16 nm (Fig. 2). Other processes were standard and compatible with 130 nm generation technology.

Source-drain extensions were deliberately non-overlapped with the gate by ~13 nm, which overcomes the problem of junction diffusion. The researchers report that traditional LDD (lightly doped drain) techniques are not effective at such small dimensions.

IEDM Highlights The International Electron Devices Meeting (IEDM), to be held Dec. 3-5 in Washington, D.C., will showcase what will be happening in electronics three to five years into the future. Six main subject areas are covered: 1) Advances in CMOS Transistor Technology; 2) The Future of Communication Devices; 3) Better Data Storage; 4) Security; 5) Emerging Technologies; and 6) Chemistry and Biology Merge with Microelectronics. Highlights in the area of CMOS transistor technology follow. For more information, see www.ieee.org/conference/iedm. Silicon on Nothing: Using the empty space in silicon (ESS) technique, scientists from Toshiba have built the first true silicon on nothing (SON) MOSFET as an alternative to the silicon-on-insulator (SOI) MOSFET. In this technique, transistors are manufactured on a thin layer of silicon suspended above empty space. They will illustrate that using this technique will lead to improved device performance by reducing junction capacitance and suppressing short-channel effects while dramatically reducing the issues plaguing previously proposed SON and SOI structures, such as the floating body effect and self-heating. Double Gate Devices: At IBM, researchers believe that, if CMOS devices are going to get faster, while still reducing in size, developers must start thinking beyond conventional CMOS devices. They will demonstrate symmetric and asymmetric double-gate FinFET devices compatible with conventional CMOS technology. These devices use a double-sided, vertical channel structure to increase device current. This paper will report the highest drive currents ever seen for the FinFET device structure, demonstrating a potential candidate for future device scaling. Merged Single Electron and MOS Transistors: By combining single-electron transistors (SETs) and MOSFETs, researchers from NTT Corp. have opened up the possibility that a new class of multiple-valued logic and SETs can be constructed with half the number of elements needed in conventional implementations. They will show how the merged SETs and MOSFETs can serve as basic components of multiple-valued logic, such as a universal literal and quantizer, which can be used create advanced analog-to-digital converters and multi-value adders.

1. A gate dimension of 16 nm was obtained by thinning down the bottom of an 80 nm gate using a selective etch process. (Source: STMicroelectronics)   2. A new record: This high-resolution TEM cross-section shows the gate oxide region of the smallest manufactured NMOSFET. The device, which operates at room temperature, was built by researchers at STMicroelectronics using conventional CMOS technology. (Source: STMicroelectronics)