High-Density Plasma Etch Processes for InP Optoelectronics

The optical telecommunications industry is rapidly expanding its network capacity to cope with the existing and projected demands for data transmission. The current trend is toward increasing the effective bandwidth by working with multiple wavelengths. Dense wavelength division multiplexing (DWDM) involves moving away from discrete optical components to wafer-scale integrated optical subsystems such as laser diode arrays incorporating multiplexing waveguide functions, waveguide detectors and high-speed modulators. The need for integration, together with increases in the number of discrete devices required on a single wafer, means that there is a move away from R&D systems toward production-worthy processes and tooling that can cope with the expected capacity. Such tooling can also offer significant process benefits such as higher and more consistent etch rates, variable profiles and better control over critical dimension and uniformity.

During the manufacture of the majority of InP-based optoelectronic devices, there is a need to etch semiconductor layers (normally including InGaAs, InP and InGaAsP, sometimes in the form of multi-quantum wells) and dielectrics (for subsequent use as hard masks or for subsequent contacting with metals). Here we focus specifically on these application areas.

All of the etch experiments were carried out on 3 in. diameter InP wafers provided by Nortel Networks. The layer structure for each process type is described alongside the results in the next section. In all cases, etching was carried out using an Omega 201 system from Trikon Technologies, fitted either with an ICP or a M0RI plasma source.

The ICP source produces a plasma with a charge density typically in the range of 10¹¹-10¹²cm^-3, and for these experiments was operated at a pressure of ~5 mTorr. All of the ICP etches involved the use of a high-temperature electrostatic chuck (ESC) set in the range of 150-180°C.

In contrast, the M0RI source produces a plasma with a charge density typically 10× higher than the ICP through the formation of a helicon plasma wave.¹ The helicon wave results from the emersion of the plasma in an electromagnetic field of ~200 G. The M0RI processes were operated at 2.5 mTorr and a conventional (low-temperature) ESC was used, set to -15°C. The ESC designs have been described in detail elsewhere.²

Ridge waveguides are used to confine optical modes as part of larger optical devices. In an active optoelectronic device, the simplest way to form an optical waveguide is to etch a shallow feature into the epitaxial layers (typically InGaAs and InP) above the light-carrying (or "active") region, typically a single layer of InGaAsP or multi-quantum wells comprising InGaAsP. The depth and lateral dimensions of the ridge are typically 1-4 µm. The desired profile will vary depending upon the subsequent processing steps, but is typically ~80-85°.

Optical mirrors are created when the etching is continued through the active layer and into the underlying material (usually InP). Here the etch depth is typically 8-10 µm and the profile must be as vertical as possible. It is also a general requirement for both the waveguide and mirror etches that the sidewall and "floor" are as smooth as possible, because roughness can lead to inefficient optical propagation.

To avoid roughness it is necessary to remove the constituents of an alloy at equal rates. A simple sputtering process would lead to preferential loss of the lightest element (P in the case of InP), and In globules would be left on the wafer. A solution to this has been to use CH₄/H₂ plasmas where the P is liberated as PH₃ and the In as In(CH₃)₃. However, the method is subject to significant limitations as follows:

• Etch rates are very low (typically 0.02-0.1µm/min for InP), making high-volume production processes impractical.
• The etch chamber and wafer are subject to significant polymerization, and there is a need for frequent plasma cleans, which greatly reduce the throughput.
• It is difficult to control the etched profile by varying the process parameters.

	1. Shallow feature in InP etched at 40°C.

	2. Shallow feature through an epitaxial stack containing InGaAs, InP and InGaAsP etched at 180°C with a profile of ~85°.

Figure 3 shows an example of a deep etch process that can be used to form an optical mirror. Here the etch depth is ~6 µm (but it is likely to be deeper in the final device), and etching proceeds through a number of epitaxial layers. The Cl₂/N₂ process at 150°C used in this case results in a vertical profile with relatively smooth sidewalls and a smooth "floor." It is particularly interesting to notice that the bottom corners of the etch form almost perfect right angles. This is unusual for such processes, where no etch stop layer is used, but is beneficial to the overall performance of the feature as an optical mirror. The InP etch rate and the selectivity to the oxide mask were 1.0 µm/min and ~15:1 for this process.

	3. Deep optical mirror etched through a stack containing InGaAs, InP and InGaAsP with a profile of 90°.

• The etch rate needs to be fast enough for a production process.
• The profile needs to be accurately controlled because this will influence either its performance as a hard mask or the subsequent metal coverage.
• The selectivity to the underlying semiconductor needs to be high enough to allow either negligible loss or a consistent loss (for hard masks).

The Omega M0RI system is better suited to dielectric etching than the ICP. The helicon wave of the M0RI produces a higher density of ions above the wafer than the ICP. Because dielectric etching relies upon significant ion assistance to the fluorocarbon chemistry (due to the strong nature of the Si-O bonding), the M0RI approach is able to achieve higher etch rates and better selectivity and uniformity control.

A sidewall "spacer" etch process is an ideal way of forming a contact to the top of a ridge (e.g. for use in fabricating ridge waveguide lasers). The wafers used for these experiments had a layer structure of ~2.5 µm patterned photoresist/2.3 µm silicon oxide/InP topography.

	4. Sidewall “spacer” etch using a two-step process.

The resulting step at the top of the ridge is <0.1 µm and the oxide profile in planar regions away from topography is ~82°, making it an appropriate hard mask. Both dielectric etch processes were endpointed by monitoring the optical emission at 440 nm (SiF*).

Practical and manufacturable dry etch processes based on high-density plasma systems have been demonstrated to meet the needs of the optoelectronics industry. ICP processes using a hot ESC have been used for both shallow waveguide and deep mirror etches. M0RI processes using a conventional low-temperature ESC have been used for dielectric hard mask open and "spacer" etching. Future work will concentrate on the benefits that these processes bring to final optoelectronic device performance.