HDIS: An Outdated Misnomer

Andy Kirkpatrick, Director of Marketing, GaSonics International -- Semiconductor International, 11/1/1998

The effective and efficient removal of implanted photoresist with minimal plasma damage to the wafer affects yield, productivity and cost of ownership. Historically, this process has been referred to as high-dose implant strip (HDIS). Up until recently, high dose has been the biggest factor in making implanted resist removal a challenge. However, new challenges in photoresist removal are emerging as device geometries shrink and new materials and manufacturing methods are introduced. Because high dose is only part of the story, the term HDIS is really a misnomer.

In ion implantation, high dose is an enabling technology for 0.25 and 0.18 µm devices. Shrinking geometries lead to decreases in gate oxide thickness, junction depth and thermal budgets. Scaled-down CMOS design rules require the reduction of junction depths, yet these junctions must also have low sheet resistance. High dose implants at very low energy are critical to form drain extensions and achieve low junction leakage currents at the 0.25 µm technology node as well as minimize dopant diffusion into the channel regions of the thinner gate oxides. However, it is well known that high dose poses challenges in the removal of implanted resist, including hardening of the photoresist surface, which makes the resist difficult to remove. Other complications include long process times, photoresist popping, oxide residues and unashed photoresist fragments, yet the solutions designed to address these issues create new problems including oxide lifting and loss.

To support the next three CMOS technology nodes (0.25, 0.18 and 0.15 µm), ion implantation has also migrated to the low dose/ high energy end of the spectrum. High energy is becoming an important trend in ion implantation, because it enables the fabrication of more sophisticated, higher performance device structures while reducing process complexity and cost. In fact, the Semiconductor Industry Association (SIA) includes high-energy in its most recent roadmap. High-energy implant systems are used in many applications, including retrograde well structures and high-dose buried layers.

Retrograde twin wells implanted after field isolation have become standard for sub-0.25 µm technologies. These structures simplify the process by requiring fewer mask levels and a lower thermal budget. They also improve isolation performance, namely latch-up control, punch-through suppression and soft-error reduction in DRAMs. However, they require up to 1 MeV energy at doses of 1 x 10¹³ to 5 x 10¹³ atoms/cm².

Another trend is the use of triple wells, which are rapidly being implemented across all CMOS technologies. These structures improve isolation from substrate noise and permit optimization of devices used for different applications on the same chip. Triple-well applications require energies up to 4 MeV at doses of 1 x10¹³ to 3 x 10¹³ atoms/cm². Because the transition to retrograde twin and triple wells eliminates two mask layers and high-temperature well drive-ins, high-energy ion implant systems are now one of the fastest growing sectors of the semiconductor process equipment business.

Despite its clear advantages, high energy also poses a number of resist removal challenges. Like high-implant doses, high energies accelerate the formation of the carbonized skin on the photoresist, which can result in photoresist popping, long process times, oxide residues and unashed photoresist fragments. Along with both high-energy and high-dose implants comes the need for higher-beam current to increase wafer throughput. As implant energies and currents increase and as new technology demands are adapted, the photoresist skin also thickens - making the prevention of photoresist removal popping even more challenging.

These higher implant currents also cause oxide sputtering, which further complicates the removal process. The resulting residues are also difficult to remove and require either the addition of a wet process step after dry photoresist removal or a fluorinated post-photoresist removal clean. However, use of a fluorinated plasma comes with a trade-off: increased oxide loss. Since smaller device geometries are characterized by thinner oxides, this loss may become unacceptable as feature sizes continue to shrink.

Clearly, the issues associated with resist removal are escalating as device geometries continue to shrink. While once relevant, the term HDIS no longer reflects the full range of challenges associated with the removal of implanted resists. In addition to high dose, high energy and high current further complicate the process. A better solution would be to remove the use of acronyms altogether, and refer to this process as simply implanted resist removal.