Defect Reduction for the 21st Century

For defect reduction and yield improvement in the 21st century, engineers face challenges of process integration that will require a new understanding of defects. Defect complexity increases, so that no one type of inspection tool will be able to fill all needs of defect inspection, classification and eradication. Areas of particular concern will include new failure modes for integrated low-k dielectric and copper interconnect systems, defect examination in contacts and vias and dopant distribution control. Stress measurements may be used as a systematic process control parameter in advanced devices. These are some of the conclusions of Rajendra Singh, director of the Center of Silicon Nanoelectronics and of Materials Science and Engineering at Clemson University (Clemson, S.C.), who presented his findings at KLA-Tencor's Yield Management Solutions Seminar in July.

According to Singh, atomic roughness of interfaces will play a critical role in determining defect type and distribution. The ubiquitous optical microscope will be gradually replaced by optical review stations and scanning electron microscopes, visible to ultraviolet inspection tools, and scanning probe microscopes.

Fig. 1. Trends relating process temperature and time in terms of stress, performance, reliability and yield.

As the industry transitions from oxynitride capacitor dielectrics in DRAMs to high-k dielectrics such as Ta₂O₅ and BaSrTiO₃, defect characterization for amorphous materials must adapt to characterize polycrystalline materials. The composition and roughness of the metal/dielectric interface in metal gates comprised of W or W_xN_y become critical. Three-dimensional doping profile

techniques will be needed to characterize shallow junctions created by solid phase epitaxy or other methods. Decreasing silicon allowance for silicides places new requirements on the quality of the silicon/silicide interface for minimal roughness. Porous low-k materials are inherently non-homogeneous in structure, unlike SiO₂. Signh explained that tantalum-based barrier materials for copper may introduce stress-related reliability concerns, and pinholes and non-uniformity-related defects in barrier layers become a greater issue below 40 nm in thickness.

Table 1 illustrates the expected extension of current patterned wafer inspection methods and the timeline for bringing new technologies into R&D phases, yield ramp-up and volume production. In the interest of minimizing thermal budget, processes must be created to reduce the activation energy and use in-situ measurements to maximize performance, throughput and yield (see Figure), especially for large diameter wafers.