Advancing Aluminum Interconnect Technology

Laura Peters, Senior Editor -- Semiconductor International, 11/1/1998

With copper interconnects stealing the headlines in the semiconductor press today, it may come as a surprise that aluminum interconnect technology is also progressing rapidly. To reach beyond capability of filling 3:1 aspect ratio features typical of traditional PVD processes, semiconductor companies are exploring many new aluminum-based interconnect solutions such as ionized plasma deposition, hot aluminum PVD and A1-CVD for traditional subtractive and possibly aluminum damascene structures. Ionized plasmas are breathing new life into sputtering technology, particularly for Ti deposition. In DRAMs, aluminum is replacing tungsten interconnects, deposited using hot aluminum, CVD/PVD combinations or traditional PVD aluminum with tungsten plugs. So while advanced logic devices such as microprocessors and fast SRAMs will inevitably transfer to copper-damascene processes within the next few years, aluminum-based interconnects, deposited by various means, will continue to dominate fab processes for at least the next five years. Some advanced aluminum stacks are enabling performance improvements and lower manufacturing cost, as the industry seeks to optimize back-end processes, the dominant cost in VLSI manufacturing.

Deposition capabilities

Conformal coverage and void-free filling of high aspect-ratio contacts and vias continue to drive advanced PVD and CVD processes. As shown in Table 1, the most dramatic aspect ratios occur at the contact level of DRAMs, at 6.3:1 for the 1G DRAM (with 0.22 µm CD) and 7.5:1 for the 4G generation (0.16 µm CD). Minimum metal linewidths today track with feature size dimensions. Barrier metal thickness is around 100 nm for the 0.25 µm generation, substantially thinner than required of the 0.35 µm generation of 400-600 nm. For 0.18 µm devices, Ti/TiN barrier layer thickness is reduced to <25 nm.

Ionized technologies (commercially offered as Ionized Metal Plasma (IMP) or Hollow Cathode Magnetron (HCM) sources) are based on in-flight ionization of atoms sputtered from commercial magnetron cathode sources, with the metal ions deposited by means of a small wafer bias. Ions arrive with a controlled energy, and a greater percentage of the sputter flux is used than in a collimated sputtering system. Ionized plasma PVD-Ti/CVD-TiN combinations are capable of producing thin barrier layers with superior via bottom step coverage relative to traditional sputtered Ti or even collimated Ti PVD. Cluster tool deposition for this application prevents the formation of TiO_x compounds at the Ti/TiN interface, which increases via resistance and affects device reliability. Commonly used TiN CVD precursors include tetrakis-dimethylamino-titanium (TDMAT), tetrakis-diethylamino-titanium (TDEAT) or titanium tetrachloride (TiCl₄).

Fig. 1. 0.35 x 1.4 µm vias are formed using the Hollow Cathode Magnetron source to deposit a 50 nm Ti layer, followed by cooling the wafer to sub-zero temperatures and depositing alumininum at 400°C. (Source: Novellus)

Several companies are using ionized plasma titanium deposition for the formation of TiSi₂ contacts with reduced contact resistance. In the interest of consolidating titanium deposition chambers in the fab, such companies are considering replacing collimated titanium sputtering systems with ionized plasma chambers to form wetting layers for hot aluminum processes. The titanium liner in hot Al deposition prevents the cold Al seed layer from dewetting. A continuous layer of titanium is essential to forming conformal aluminum films and preventing aluminum agglomeration (Fig. 1). Ionized plasma PVD of Ti may also enhance the growth of (111) oriented AlCu grains for improved electromigration (EM) lifetime.

Tungsten CVD processes will change little, though people are examining lower temperature (370°C) processes. For cost and performance reasons, DRAM manufacturers are interested in replacing tungsten interconnects with aluminum if a process can fill the high-aspect-ratio contacts. Ionized plasma Ti/TiN processes might come into play here, and Al-CVD may be used to fill high aspect ratio features just enough, followed-up with a sputtered aluminum (at 380°C) to complete the interconnect. Such two-step processes simplify the doping of aluminum needed in all-CVD processes. Alternatively, ionized plasma PVD aluminum might be used to deposit a wetting layer, followed by traditional PVD fill. Cost-of-ownership will drive the development of these DRAM processes.

Hot aluminum processes typically involve two steps, a cold sputtering step (wafer temperature of 0°C), followed by a high temperature deposition at 370-425°C. A hot Al process saves three process steps for each metal layer compared to W plug processes, reducing the number of process steps and lowering manufacturing cost. Prior to deposition, the via profile is typically rounded using an in-situ RF etch with inert gas in the metal PVD tool. The cold step improves hole filling and mobility of the deposited aluminum, while the hot step flows the aluminum. Hot aluminum processes are being extended by lowering process temperature and reducing chamber pressure to fill 6:1 aspect ratio features.

Blanket CVD of aluminum is typically deposited using the dimethyl aluminum hydride (DMAH) precursor. Copper doping can be performed in-situ using a copper CVD precursor (such as (C₅H₅)CuP(C₂H₅)₃), or by post deposition of Al-Cu or Cu followed by a diffusion step. Al CVD might possibly be used in aluminum damascene structures, an approach that alleviates problems with metal etch and issues of planarizing any of a variety of low-k dielectrics over etched metal. Following sputtered Ti/TiN deposition, the wafers are often treated with a hydrogen plasma to improve nucleation, then transferred under vacuum for Al or Al/Cu/Al CVD at around 200°C. Al-CVD can fill trenches with 5:1 aspect ratio or higher. Selective Al-CVD, a less-likely alternative, provides even lower via resistance, because the barrier metal at the via bottom is eliminated. Despite the report of successful fabrication of 1G DRAM structures using an aluminum damascene structure¹, widespread adoption of aluminum damascene processes is not expected due to the immaturity of aluminum CMP processes and the rapid transition to copper damascene structures.

Vias continue to be the weak link in the interconnect system, placing greater importance on barrier metal stability. In terms of reliability, device scaling drives the need for higher design current densities and necessitates improvements in EM performance. One way of compensating for these higher current densities is to add more copper to the aluminum (above the standard 0.5 wt%). Indeed some companies are using aluminum with copper concentrations as high as 2 wt%, yet any level above 0.5 wt% carries with it resistivity penalties. Alternatively, Ti and TiN capping layers over the aluminum improve EM performance.

Etching capabilities

High-density plasma systems are capable of balancing components of chemical etch, physical bombardment and passivation needed to etch sub-0.35 µm features. Success of a metal etch process is measured in etch uniformity, profile control, CD control, anisotropy, selectivity to photoresist and selectivity to underlying oxide. Metal etching is often a game of tradeoffs - between residue removal, resist loss, or profile and microloading. Microloading refers to the faster etch rate in wide spaces relative to densely patterned regions.

Fig. 2. Nominal metal stack for a 0.18 mm process.

Aluminum etches typically use BCl₃/Cl₂ chemistry with N₂ added for sidewall passivation. In addition to tight CD control, key metal etching concerns today include selectivity to photoresist, damage prevention, corrosion prevention and control of microloading (to <8% across the wafer). Aspect-ratio-dependent etching (ARDE), the faster etching of material in shallower features relative to high-aspect-ratio features, is also a growing concern as the industry progresses to smaller feature sizes. Addition of CHF₃ to the traditional etch chemistry can reduce ARDE, though manufacturing data on CHF₃ use are currently limited.

Damage from high density plasma etching - induced by non-uniformities in the plasma, pattern-dependent charging or other means - can occur using any of the various platforms (ICP, helicon, ECR, etc.), making the monitoring of plasma density and plasma uniformity absolutely essential. Operation in the highest plasma density range of the etcher probably increases likelihood of damage. Following etch, sidewall residue removal is a critical challenge. The sidewall films typically contain organic material from the etchant and resist mask, but also metallic and other inorganic compounds. Microwave downstream plasma removal appears to be the method of choice for these residues, often followed by a wet solvent treatment. Ultimately, users would like integrated etching and stripping processes that simply require a DI rinse following the ashing step.

Fig. 3. Al interconnect etch with in-situ organic ARC (top) and in-situ SiON ARC etch (bottom) for sub-0.18 µm devices. (Source: Lam Research Corp.)

At 0.18 µm, metal etch is challenged by the decreasing depth of focus available with DUV lithography processes, shrinking resist budgets and increasing need for metal reflection control. As a result, various modifications of the traditional Ti/TiN/Al-Cu(0.5%)/TiN stack are being created (Fig. 2). For instance, companies are now using either organic or oxynitride antireflective coatings on top of the Ti/TiN barrier (Fig. 3). It appears as if the dielectric-based ARCs will be preferred in production due to better process latitude. As an alternative to using DUV resist masks, some companies are using hard masks in place of the resist, etching the dielectric in one chamber, directly followed by metal etch. The resist can also be stripped after dielectric etching and before metal etching. All these schemes are being considered as metal lines approach 0.22-0.25 µm at 0.18 µm design rules.

Etching of thicker barrier metals, required in multilevel metal stacks, can consume a good portion of the resist budget for 0.18 µm devices. Selectivity to resist for TiN is between 2:1 and 1:1, a poor performance relative to aluminum, typically between 3:1 and 4:1. Therefore, even though the TiN layer is thin, its etch process can consume a substantial amount of resist.

Tungsten-based interconnect etches and tungsten etch-back processes constitute a sizable portion of the overall metal etch market. This trend will continue as contact aspect ratios for DRAMs increase from 5.5 for 0.25 µm devices to 6.3 and 7.0 for 0.18 and 0.15 µm generations. At the same time, DRAM chip manufacturers are making the transition from tungsten interconnects at metal 1 and 2 to tungsten metal 1 and aluminum metal 2, eventually progressing to tungsten plugs and aluminum metal 1 and 2, for the 256 Mb generation. In this case, companies that can supply a platform accommodating either tungsten or aluminum etch can enable a lower-cost transition from tungsten interconnects to tungsten plugs with etch-back. Such approaches might also delay the use of tungsten CMP until the 1 GHz DRAM generation or later.

References

1. P. Singer, 'Dual-Damascene Aluminum Process Developed,' Semiconductor International, Aug. 1998, p.46.