300 mm Overcomes Critical Hurdles

		At a Glance
	Although meeting most 300 mm requirements has involved straightforward scaling from lessons learned at 200 mm, the introduction of copper and exotic low-k materials demands the redesign of chambers, a search for possible alternatives to traditional CMP, and an unparalleled application of integrated metrology.

"For copper processes, one of the most important inspection applications is partitioning defects in the wet room between copper electroplating and CMP," said Pete Nunan, vice president, strategic alliances at KLA-Tencor (San Jose). "CMP tends to reveal void-related defects from previous processing steps such as CVD seams (tungsten-plug coring) and electroplating fill defects. Without the ability to partition, determining the source of these defects would be impossible."

Wilbert van den Hoek, executive vice president of integration and advanced development at Novellus Systems (San Jose), does not view 300 mm as a technology challenge. "When we scale up we must maintain uniformity and film properties across the wafer's diameter. So far, this has been straightforward."

According to Dan Koharko, vice president and general manager of substrate, storage and optics at Rodel (Phoenix), 300 mm is ramping up slower than the demand would justify. "Substrate houses cannot get return on capital, and it's very costly for them to make new 300 mm manufacturing sites. All the leaders — Sumitomo, Mitsubishi — are doing it, but on pilot lines and at a slower pace than CMP's ramp-up to 300 mm."

1. Successful 300 mm processing demands unparalleled control at all levels of the processing platforms, particularly with the introduction of copper and exotic low-k materials. (Source: Applied Materials)

Stuart Tyson, director of metrology and applications for Mykrolis (formerly Millipore Microelectronics, Bedford, Mass.), believes the less obvious hurdles associated with the move to 300 mm are process-associated scaling issues. "Increasing device complexity and multiple layers complicate film property changes induced by subsequent processing. These effects must be addressed, particularly across-wafer uniformity. Process chamber design, pumping uniformity, wafer temperature control and chemistry all play roles in ensuring wafer uniformity for etch and thin film."

Resist and etch concerns

Applied's Mah considers photoresist selectivity a challenge, especially with photolithography technology moving to 193 and 157 nm for critical layers. "Achieving CD goals, especially for litho-critical front-end applications through 193 and 157 nm technologies, results in thinner resists with reduced etch resistance," she said. "This negatively impacts the resist budget for etch processing, placing challenges on most aspects of dielectric etch from CD to profile control."

For 100 nm, these challenges are being met by the combined optimization of reactor design and etch chemistry. "For 300 mm eMAX, the chamber was tailored to run more polymerizing etch chemistries for high selectivity," Mah said.

Neil Hanson, Applied's director of silicon etch, still views 0.15 µm, or 0.12 µm etch gates, as state-of-the-art for 300 mm. "Gate length has departed from the generation cycle in logic," he said. "Manufacturers are running 70 nm gates with 110 nm technology. The problem is that many transistor design steps aren't finalized. Nobody knows whether we'll go to vertical-gate, or exactly when we go to tungsten gates. Then, will it be tungsten on poly, on TiN, straight to oxide? Then when do we go to tungsten on high-k? Then which high-k will you use for the gate dielectric — some kind of aluminum oxide or silicates?"

Applied recently introduced its DPS II 300 mm family. "We've had 300 mm products for years," said Hanson. "The second wave began a year ago with 0.15 µm and must extend to 0.10 µm. We had to ensure we had a flexible reactor."

Most first-generation 300 mm reactor systems use inductively coupled plasmas for poly and metal etch. "This works well at 200 mm," said Hanson. "It uses a bias power and source coil above a dome or window. The problem's that the coil's position establishes plasma uniformity and you cannot change it, the process pressure, or the chamber's height. And depending on what you're doing, these must change."

Applied's chamber has a two-coil tunable source over which to split power, ensuring plasma uniformity across a wide pressure range, as well as a wide gas and species range. The new source provides <10 nm CD bias uniformity on 300 mm.

A critical issue is wafer-edge performance. "You want CD control all the way to the wafer's edge," said Ralph Kerns, Applied's general manager of metal etch. "CD control has been in the 10% range for metal etch — not as critical as gate etch because of the speed dependence on gate etch, which doesn't directly translate to metal etch. We're talking about 5% or better CD control and have demonstrated it as low as 3% 3 sigma."

Kerns added that, for large die on a 300 mm wafer, the challenge is getting yield out to 3 mm — soon to 2 mm. "This is for all integration steps — doing it just for etch is insufficient."

Ben Bierman, Applied's managing director of thermal systems and modules, focuses on single-wafer solutions for front-end transistor steps. "Difficulties lie in the 0.13 and 0.10 µm nodes, not in wafer size. We have demonstrated the scalability of our processes such as ultrashallow junction spike anneals, silicon nitride, poly deposition, ISSG oxides and nitrided oxides for gates, at key strategic sites."

According to Bierman, gates will change the most. "We've users running plasma nitridation at 18 Å, and they plan to scale to 16, 14 Å— even 12 Å— and must extend this to 10 Å. Each 1 or 2 Å oxide thickness reduction — while keeping leakage under control — is difficult. However, toolset scalability is definitely enabling technology."

Ultrashallow junctions will not get easier. There are toolsets with fast ramp-up capabilities, and a ramp-down capability of 90°C/sec. "You're above the critical process temperature within 50°C of peak for about 1.6 seconds depending on the peak temperature," said Bierman. "Recent improvements without any significant chamber design shows 24% improvement in the thermal budget of the spike profile."

By adjusting the implant and pushing the tool's ramp-up and -down rates to the limit, conventional RTP technology can meet 0.10 µm junction depth requirements. At 70 nm, the industry may hit the wall. Laser annealing and other alternatives are being considered.

Steve Lassig, senior integration manager for Lam Research (Fremont, Calif.), views etch scaling as both a process and systems issue. Lam has used a fundamental approach to understand gas flows, plasma uniformity and thermal characteristics. Extensive use of computer modeling has allowed optimization of Lam's 2300 line of etch systems, including a balanced gas injection system and other modifications. "These changes effectively increased across-wafer performance and reduced edge exclusion to below 3 mm," Lassig said.

Dave Dutton, president of the Plasma Products Division of Mattson Technology (Fremont, Calif.), sees an equipment size vs. quality struggle. "Uniformity will continue to be a key issue, particularly as we get to thinner films. For 300 mm we have pushed the wafer-size-to-chamber ratio toward 1 to keep the equipment footprint smaller. With plasma reactors, this makes it more difficult to achieve the uniformity required. Focus on the plasma uniformity has become a larger factor in the design of 300 mm plasma reactors, as space becomes a premium."

David Duff, marketing director of Axcelis's ion implant and thermal processing systems group (Beverly, Mass.), believes 300 mm requires a control-oriented approach. He uses its RTP system as an example. "We use a silicon carbide bell jar surrounded by furnaces to create a black-body-type environment, which is a quasi-thermal equilibrium with the wafer. We then predictively control the position of the wafer in z to its corresponding sweet spot for a given process. Thermally, this approach is inherently more stable, compared to a lamp-based one allowing for feed forward control approach."

Axcelis takes different control system approaches for different implanter toolsets. "By using a fixed beam and mechanically scanning the wafers for high-energy and high-current applications, we get a more stable and predictable processing environment," Duff said. With a fixed-beam configuration, closed-loop dosimetry control of the beam over the entire wafer is maintained continuously.

"Front-end technology issues revolve around gate dielectric thinning, its eventual replacement with a complementary electrode, and channel engineering," said Robert Brown, strategic account manager at Tokyo Electron Ltd. (Austin, Texas). "Back-end development issues revolve around copper, barrier/liner and low-k material integration issues as well as increased complexities in metal interconnect."

Research shows that some form of SiO₂ will suffice to the 70 nm node. Beyond, mid-k and high-k material selection must address electrode compatibility, metrology and integration issues. Processing challenges with respect to the channel revolve around ultrashallow junction control. Lateral abruptness with low series resistance requires well-controlled doping and annealing. As lateral and depth abruptness become more critical, especially below 100 nm, alternative annealing techniques may be required.

Metrology considerations

Roger Ingalls, vice president and director of marketing for Nanometrics (Sunnyvale, Calif.), believes metrology is no longer viewed as a "necessary evil." "Mistakes have become more costly, and there's where metrology fits in," he said.

Larger wafers require additional metrology. "Before, you'd measure five to nine sites per wafer," Ingalls said. "With 300 mm you must do nine to 17 sites or more."

The closer metrology is to the process, the faster the throughput and the faster you can detect process excursions. This can be accomplished through the use of integrated metrology. "To increase metrology throughput, we've gone to rotating stages and changing the design of the traditional x-y stage by eliminating one axis and rotating wafers to get complete wafer coverage," Ingalls said.

Nanometrics concentrates on "universal" IM platforms. "We design plug-and-play sensor or metrology modules, whether it's for film thickness, copper or CD metrology," Ingalls said. "The sensor is plug-and-play but the platform remains the same. This makes it easier to integrate one IM platform — whatever metrology the process tool provider requests — that plugs into the appropriate sensor."

Initially, some major players thought it impossible to get the same sensitivity using IM's smaller units, believing sensors were not as good. This was not the case — IM sensors are as accurate and precise as those for stand-alone metrology.

Giora Dishon, president and CEO of Nova Measuring Instruments (Rhovoth, Israel), agrees that IM has a central role in 300 mm processing. "Although some technologies and systems aren't available yet for some applications, they're taken into account in planning," he said, adding that key processes requiring IM are lithography, etch, CVD, CMP and ECD. "Currently, working IM state-of-the-art is in two measurement areas: thin film and overlay." As it evolves alongside semiconductor technology nodes, IM equipment will provide the same or better measurement quality as stand-alone metrology in the much less friendly environment of process tools.

CMP and process monitoring

KLA's Nunan views pattern transfer as a big step and etch residue as a major contributor to yield losses in the copper process. "Inspection of via voiding is all e-beam and voltage-contrast-based. If you aren't inspecting that way, you'll never see enough vias to uncover the source of the yield loss."

Etch residue affects pattern transfer. The litho challenge of putting down a pattern has not changed. Dimensions have shrunk in the back end, but are nowhere near where front-end dimensions are. Eighty percent of yield drop-out is related to the back end.

"Copper film is grainy, yet it's critical to determine if defects are post-polish — polish or plating defects," Nunan said. "A dark-field grazing incidence angle tool works well on plated films because it suppresses much of the grain noise. Aligning isn't easy because you get a hazy pattern and it's difficult to do pattern alignment on it. However, once this defectivity is characterized in plating tools, it's simple to determine what to change."

KLA designed an endpoint detector that tracks the wafer during CMP. "When the sequence is initiated, it passes over the sensor in real-time polish speed, so that if you're doing 30 rpm every two seconds you can make a full-diameter scan wafer measurement. It's scanned with an eddy current probe, past the wafer's full diameter on the polish heads," Nunan said. "This provides actual thickness across it, making it possible to calculate nonuniformity, track uniformity degradation if the polisher is working improperly, or determine removal rate to increase or reduce the down force, or change slurry flow."

Below 500 Å there is insufficient film for accurate measurements. "Then we switch to optical and you can see the actual copper clearing," Nunan said. "This is a tight process window — underpolish leads to copper/barrier residue which causes electrical shorting; overpolish leads to erosion. Erosion of previous-level metal leads to bridging or shorting of subsequent metal levels commonly referred to as "copper pooling."

For Novellus, wafer scaling enabled the development of its second-generation 300 mm tools. "From our work on 200 mm platforms, we found there's a need in dielectrics deposition for integrated processing, using the same equipment configuration," said van den Hoek. "A modular architecture with multiple process chambers is expensive. At 300 mm we view copper as the main technology, using damascene dielectrics. Since damascene films are deposited in a planar fashion, the same chamber can be used for multiple film types, reducing the need for multimode cluster tools."

Van den Hoek believes the mechanical properties of dielectric materials with a k of 2.0 and below will be incompatible with conventional CMP. Alternatives would be electropolishing or wet chemical etching. Both require a completely flat plated copper film. This is viable if all lines are less than 20 µm wide. Although 95% of them are, the 5% that are not would require design changes.

2. Mechanical properties of dielectric materials may be incompatible with conventional CMP. Alternatives are electropolishing, wet chemical etching, or a design change to allow planarization. However, this might turn an eight-layer device enabled by CMP in to a nine-layer interconnect device enabled by the other methods. (Source: Novellus)

Lam's Rod Kistler, managing director for CMP/clean technology, agrees there is uncertainty regarding continuing CMP in its traditional role for ultralow-k materials. "As we get to constants below 2.6, we introduce porosity to 20-40% in the film and, as a result, their mechanical integrity is significantly lower than their conventional SiO₂ counterparts. Our experience shows that downforce and polish speed are critical, impacting CMP performance for new ultralow-k materials."

Process monitoring is crucial, according to Dan Trojan, copper program director for SpeedFam-IPEC (Chandler, Ariz.). "Everything was done blindly in CMP, based on time, predicting, and targeting endpoint time. Then came in situ endpoint detection, which was optically based, motor-current-based, or maybe eddy-current-based."

Trojan added that, as bulk copper is cleared down to the underlying topography, the clearing sequence must occur as uniformly and simultaneously as possible. "For this you need process monitoring with resolution beyond just a global indication of endpoint detection across the wafer," he said. "Our system uses multiple discrete zones — different numbers depending on options — to maintain an adequate level of real-time resolution. It's possible to determine globally when you've reached endpoint across the entire wafer. You can also determine the relative rate of clearing on each individual zone and the overall span of time at which the different zones across the wafer are clearing."

Consumables and 300 mm

In exploring abrasive-free processes, SpeedFam discovered there is a trade-off in using conventional consumables between planarization performance and metal and oxide loss. With conventional consumables today's requirements can be met at 0.13 µm, but it is a stretch to extend this process to 0.09 µm and beyond. Using abrasive-free slurries, SpeedFam has demonstrated results exceeding copper loss specifications for 0.09 µm at the intermediate and global interconnect levels.

Mario Stanghellini, Rodel's vice president and general manager for Rodel's CMP business, believes 200 mm consumables — slurries, pads and conditioners — are transferable to 300 mm. "Consumable sets will be the same as the toolsets, but when something expands 2 or 2.5 times, there are performance changes."

3. Most 200 mm consumables are transferable to 300 mm, but not everything scales linearly. A wafer area 2.5× greater than that of 200 mm will require a greater use of consumable sets, as well as resulting in some transition variables. (Source: Rodel)

"The transition to 300 mm has significant implications for the manufacturers of process gases," said Joseph Stockunas, worldwide marketing director, Electronics Division, Air Products and Chemicals Inc. (Allentown, Penn.). "Process gas volumes for 300 mm are about three times those for 200 mm."

Specialty gas flow rates for 300 mm fabs are expected to increase over typical 200 mm values. "For 300 mm, large-volume gases such as NF₃, N₂O, NH₃, SiH₄ and HCl are best supplied using bulk specialty gas supply systems," Stockunas said. "Additional supply considerations, like heated cylinders and heat-traced lines, may be needed." Gas purity levels will depend on design rule rather than wafer size. However, users will demand cleaner specialty gases as they develop more sophisticated designs.

Mike Fury, R&D and engineering vice president at EKC Technology (Hayward, Calif.), believes chemical formulators must tailor chemistries, not only for specific applications but for specific equipment. "Where manufacturers use dip tanks, they have batch processing, longer process times, and use mild chemistries to preserve CDs both for metal lines and vias," he said. Conversely, with the trend toward single wafer accelerated by 300 mm, this processing requires high throughput and aggressive chemistries.

"That scenario requires shorter contact times between chemistry and wafer, enabling more aggressive, tightly controlled chemistries," said Fury. A new dual-chamber configuration from TEL allows a sequential use of chemistries: In a process step an aggressive chemistry may be needed, followed by a quench step. "Our tool is a batch processor with the potential to turn chemistries on and off. Another feature common to closed spray tools is atmosphere control. Some corrosion chemistries pose problems in ambient, but in a nitrogen-saturated environment without oxygen become tolerable. Sometimes you can even use CO₂ to lower pH and control corrosion."

Scaling up power

According to Joe Monkowski, senior vice president, business development at Advanced Energy Industries (Fort Collins, Colo.), power requirements scale up with wafer area. "Increasingly, power supplies are going on the tool rather than separately, so we're focusing on density — more power in less volume." Another requirement is for tighter process control. "With so many process variables, equipment manufacturers want to minimize the more standard parameters. The requirement is for tighter process control, temperature measurement, temperature control, mass flow control and rapid response." An example from the power arena of the need for more rapid response is the move to solid-state matching networks from traditional mechanical tuners that take a second or more to come to the desired power level.

Lithography and materials

Art Zafiropoulo, chairman and CEO of Ultratech Stepper (San Jose), believes that, because the mechanization of shifting from one wafer size to another was done years ago, the process is the only major change. "The process was programmed for 0.25 µm, and they're now scheduling it for 0.13, 0.10 µm, so reactors are changing to accommodate that difference."

On the technology side, Zafiropoulo sees concern areas below 0.10 µm. "One is the formation of shallow junctions, the second is the availability of calcium fluoride for optics. As we move to 157 nm, optics must be 100% calcium fluoride, and its availability is limited. Materials could limit the expansion of 157 nm and that's lithography's biggest issue."

Materials are every technology's downfall. The current solid-state revolution will end when transistors no longer work at a specific geometry or physical orientation because of materials.

In 20 years or so, the next step will be from solid-state to chemical reactions. These will be 3-D structures. It is yet to be determined how this cube would be accessed to get information out of it, possibly with some sort of laser. That will have to be resolved before this move takes place.

Static Charge Challenges in the 300 mm Regime Larry Levit, Director of Technology, Ion Systems, Crystal City, Mo. Static charge is a serious drawback to efficient semiconductor manufacturing. Electrostatic attraction (ESA) — caused by the electric field from charged wafers — draws particles out of the air, defeating contamination protocols (Figure). Discharges between objects cause electromagnetic interference (EMI) transients that find their way into the microprocessors that drive robotics, confusing them, resulting in lower tool availability. Additionally, stray fields from charged objects in the fab induce potential differences between reticle features and lead to electrostatic damage (ESD) and sudden yield drops. In a 300 mm fab, static charge generation will not be dissimilar while the same processes are taking place, resulting in the same levels of triboelectric charging. However, the static charge effects where the size scale of wafers, FOUPs and processing tools move up to 300 mm are profound. The reasons are outlined below. Static charges can be disastrous to yields in semiconductor processing. ESA contributes to contamination, EMI can disrupt tool function, and ESD caused by potential differences can cause yield drops. (Source: Ion Systems) ESA — ESA theory is well understood.1 It models the electric field from a charged wafer, with appreciable effects up to a one-wafer-radius distance. A 300 mm wafer with a given charge density thus acts on particles 50% farther away than its 200 mm counterpart. So a 300 mm wafer will exhibit a larger amount of contamination from ESA than a 200 mm wafer.2 As a result, 300 mm wafer fabs face greater contamination control challenges than their 200 mm predecessors. EMI — The FOUPs or wafer storage containers that are used for 300 mm wafer processing are large, insulative plastic containers. Measurements made in pilot 300 mm fabs show that FOUPs charge easily. As they move through a bay, their electric field travels with them. As the field contacts objects in the room, they acquire a voltage and, in some cases, produce a discharge. Studies have shown surprising levels of EMI measured. Direct discharges from 300 mm wafers have also caused tool shutdowns at SEMATECH.3 ESD — Unfortunately, ESD damage to reticles is common. However, this is not expected to worsen with the larger wafer size. Until new chip designs with smaller feature sizes become available, reticles will be no worse off than with 200 mm processing. Chips on the wafer will remain just as secure as in the past until designs move to thinner gate oxide layers. REFERENCES R.P. Donovan, "Controlling ESA of Particle in Production Equipment", Semiconductor International , July 1999. L. Levit, T. Handley, F. Curran, "In 300mm Contamination Control, Watch Out for Electrostatic Attraction," Solid State Technology , June 2000, p. 209. C. Murdock, "300 mm Stepper ESD Issues/ Resolution Using Alpha Particle Ionizers," Workshop on Electrostatic Discharge Impact and Control, Austin, Texas, International SEMATECH, October 2000.