Calculating Wafer Tester Yield Limits

Laura Peters, Senior Editor -- Semiconductor International, 7/1/1999

Part 6 of Series

Part six in this series of articles on Integrated Yield Management by Nick Atchison and Ron Ross of Silicon Systems (Santa Cruz, Calif.) introduces an automated method for calculating yield loss due to wafer test equipment variations. It determines random losses (Y_D) due to hardware or software-related noise as well as systematic losses (Y_S) related to a malfunction or miscalibration of a specific unit of tester hardware. This article is one of several subsequent papers to 'A Comprehensive Sequential Yield Analysis Methodology,' summarized in Semiconductor International's January 1999 issue. This portion addresses the second level of the IYM triangle, calculating probe yield limits due to tester hardware.

Calculation of Y_S requires two types of data for a given time period: probe data (Table 1) and utilization data (Table 2) describing which tester, swap block, probe card, etc. was utilized in the testing of each lot of wafers. The highest yielding equipment setup (combination of tester, probe card, load board, etc.) is used as the basis for optimum yield performance. Only frequently used hardware units should be used to calculate maximum yield, and the highest yielding unit must have processed at least 20% of wafers during the time period. Ross and Atchison found a statistical sample of 600 wafers was sufficient with a probe yield standard deviation of 6%. The calculation is repeated for each type of equipment. In this example, probe cards caused the greatest yield loss. Improved card cleaning and calibration improved yields. By sequentially trouble-shooting and repairing the worst-case equipment setup, equipment yields can be continually improved.

Random yield loss calculations require only wafer yield maps of the correlation wafer, run repeatedly (>10X) to verify test system performance. By stacking the maps using Excel or DataVision databases, yield limits are computed. If a die tests good once, it is considered a functioning die. In this example, cluster analysis identified tester instability regarding a sequence of the on-chip power supply 'power up' position. Atchison and Ross corrected the problem by placing diodes across the power supply tester pins to ensure even power supply start up. Y_D failure rate analysis can also indicate which tests can be moved to final test to eliminate test instability.