Tin for No-Lead Solder
John Baliga, Associate Editor -- Semiconductor International, 7/1/1999
Mitsubishi
Electric Corp. (Tokyo, Japan) announced two
products that combine 16 Mb of flash memory with 2 or 4 Mb of low-power
static random access memory (LPSRAM) in a surface-mountable stacked chip
scale package (S-CSP). The package is 8u11 mm with a 0.8 mm ball pitch.
IXYS
Corp. Orient
Semiconductor Electronics ASM Pacific
Technology, Ltd. Intel
Corp. Xilinx
Electroplating
Chemicals and Services (ECS, Staten Island, N.Y.), a division of Lucent
Technologies (Murray Hill, N.J.), has developed an electroplating process for
tin that can be used in lead-free soldering applications. The SnTech (pronounced
'tin tech') process addresses concerns about whisker formation.
Company News
Polymer Flip Chip
Corp.
opened a new 35,000
ft2 facility in Billerica, Mass. Equipment is in place to
perform up to 30M chip placements per year using the company's conductive
polymer bumping technology, and the company plans to triple that capacity
by the end of the year. The company also signed a licensing agreement with
Navitas
Corp. (Asaka, Japan) to develop smart card
and wireless communication devices.
(Santa Clara, Calif.) recently
received UL approval for its internally isolated TO-247 outline power
package. The ISOPLUS247 guarantees a minimum of 2500 V(rms) isolation
between the back of the package and the silicon chip and its leads.
(OSE, Kaohsiung,
Taiwan) recently bought preferred stock in Integrated Packaging
Assembly Corp. (IPAC, San Jose, Calif.) worth 75%
of IPAC's common stock.
(Hong Kong) received an order
for 100 AB339 gold wire bonders from a leading Taiwanese semiconductor
assembly company.
(Santa Clara, Calif.) recently announced
its Stacked-CSP, in which flash and SRAM memory are stacked. The company
initially will offer 16 Mb flash/2 Mb SRAM and 32 Mb/4 Mb SRAM
combinations in the 8 u 10 mm, 72
ball, 0.8 mm pitch package.
(San Jose, Calif.) recently announced 144- and
280-ball, 0.8 mm pitch CSPs for its SpartanXL FPGA and XC9500 CPLD
families. New 1.0 mm FinePitch BGAs ranging from 256 to 680 balls also are
available for Virtex FPGAs, as is a 144-ball CSP for the two smallest
Virtex devices.
The crystallization of tin, or whisker formation, is one of the reasons people have been slow to use pure tin as a solder material or final finish layer, because the whiskers can cause short circuits. This is due to the small grain size, typically ~0.1 µm. Small internal forces are enough to force tin's aging process to take the form of whiskers. ECS researchers found a way to increase the average grain size by reducing the organic content of the deposited tin and using chemistry appropriate for large tin grain formation.
Keeping the organic content down has numerous advantages. First, it lowers the number of intranode stress points, or nucleation points, for grain formation. This reduces the number of grains, which increases the average grain size. Second, the presence of organics inhibits grain growth, so reducing the organic content allows grains to grow larger. The presence of organics in the finished tin film also adds to the stress in the film, so lowering the organic content makes the film more stable.
The organic chemicals in the plating solution are formulated so they are not incorporated in the plated tin. Typical military requirements for organic content are l 0.05%, and some commercial plating processes have a higher organic content. The resulting film using the SnTech plating process has l 0.004% organics. Typical grain sizes using this process are ~5 µm.
The resulting material also has demonstrated good solderability and reflowability, making it suitable as a solder material. The company also reports that the film has good ductility. Fairchild Semiconductor and International Rectifier are testing the process.
The 1997 NTRS roadmap identified the reduction of lead content in lead finish
and bumping applications, and the 1999 National Electronics Manufacturing
Initiative (NEMI) roadmap identified the reduction or elimination of materials
of concern, like lead, as an area of activity in the next five years.
Matrix Testing Increases Throughput
Credence Systems Corp. (Fremont, Calif.), Fico b.v. (Zevenaar, The Netherlands) and Amkor Technology (Chandler, Ariz.) have developed a method for testing flash memory devices in a matrix strip before singulation from the leadframe or the strip. Amkor integrated a KALOS non-volatile memory test system with a Fico strip-based test handler to improve test throughput.
Amkor has been using the combination of KALOS and the Fico test handler since February at its facility in Manila, Philippines. Amkor eventually hopes to test 50 devices in parallel using this combination.
Credence estimates matrix testing can reduce capital cost and floor
utilization up to 30% and index time up to 50%. This method can be used for any
device type or package type assembled in strips.
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